FinFET Gate Stack Formation Without Dummy Gates
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Solution Overview
Problem
The semiconductor industry faces challenges in simplifying the manufacturing process of transistors, particularly in forming gate structures without the need for dummy gate structures, which complicates the process and increases costs.
Innovation Solution
The proposed solution involves depositing an interlayer dielectric directly on channel and source/drain regions of a substrate, etching openings to expose the channel regions, and then depositing layers of gate dielectrics and electrode materials to form gate stacks without first forming dummy gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy gate structures are formed prior to gate structures, then the gate structure formation is enabled, but the process complexity and manufacturing cost increase
Solution Approach 1:
The patent removes the dummy gate structure formation step from the conventional transistor manufacturing process. By directly forming gate structures on channel regions without intermediate dummy gates, the process flow is simplified while maintaining functional performance. This extraction of unnecessary components directly reduces manufacturing complexity and cost.
Solution Approach 2:
Instead of following the conventional sequence of forming dummy gates first and then gate structures, the patent inverts the approach by directly forming functional gate structures on channel regions. This reversal eliminates the dummy gate step entirely, simplifying the overall manufacturing process while achieving the same functional outcome.
2Ease of manufacture
If dummy gate structures are formed, then gate structure formation is enabled, but manufacturing cost increases
Solution Approach 1:
The patent eliminates the dummy gate structure formation step, which removes the associated material consumption (polysilicon deposition, patterning materials, etch chemicals) and processing costs. By extracting this unnecessary step, manufacturing costs are reduced without affecting the functional gate structure formation.
3Manufacturing precision
If thin sidewall spacers are formed, then manufacturing defects are reduced, but processing precision requirements increase
Solution Approach 1:
The patent forms sidewall spacers on the channel regions before forming the gate structures. This preliminary action establishes precise geometric constraints that guide subsequent gate material deposition, ensuring uniform thickness and reducing manufacturing defects. The pre-formed spacers act as templates that control the final gate structure dimensions.
Solution Approach 2:
The sidewall spacers serve a dual function: they define the gate structure geometry and simultaneously protect the channel regions during processing. This self-service approach reduces the need for additional protective measures and minimizes processing-induced defects while maintaining precise dimensional control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process flow, reduces processing complexity, and lowers manufacturing costs by eliminating the need to pattern high aspect ratio dummy gates, while also allowing for the formation of thin sidewall spacers that reduce manufacturing defects.
Implementation Method 1
an interlayer dielectric (ILD) may be deposited directly on channel regions and source/drain regions of a substrate
Implementation Method 2
an interlayer dielectric (ILD) may be deposited directly on channel regions and source/drain regions of a substrate
Implementation Method 3
The ILD may then be etched to define openings exposing the channel regions
Implementation Method 4
The ILD may then be etched to define openings exposing the channel regions
Implementation Method 5
various layers of gate dielectrics and gate electrode materials may be deposited in the openings, thereby forming gate stacks
Implementation Method 6
various layers of gate dielectrics and gate electrode materials may be deposited in the openings, thereby forming gate stacks
Data Source
AI summary
A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.