FinFET Gate Stack Etching for Multi-Threshold Fin Protection

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Solution Overview

Problem

Existing FinFET technologies face challenges in forming multiple threshold voltages without damaging the fin structure during etching processes, leading to leakage paths and performance issues.

Innovation Solution

A method involving the formation of a first interfacial layer over the fin structure, followed by a gate dielectric layer and a sacrificial layer, where an anisotropic etching process changes the etching characteristics of the gate dielectric layer, allowing for isotropic etching to remove the sacrificial layer and expose the interfacial layer, which is then protected by a second interfacial layer, enabling the formation of different work function layers without damaging the fin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional etching processes are used to form multiple threshold voltages, then work function layers can be differentiated, but the fin structure is damaged and leakage paths are created

Engineering Contradiction:

Improvemultiple threshold voltagesVSAvoidfin structure integrity

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

A sacrificial layer is introduced as an intermediary component between the gate dielectric layer and the fin structure. This sacrificial layer enables selective removal of the gate dielectric layer in specific regions to form different work function layers, while the fin structure remains protected throughout the process. After the gate electrode is formed, the sacrificial layer is removed, achieving the desired multiple threshold voltages without damaging the fin structure.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial layer is formed in advance before the gate dielectric layer and gate electrode are deposited. This preliminary action establishes a protective framework that guides subsequent etching processes, ensuring that the fin structure is not exposed to damaging etchants until the gate electrode is already in place and can provide protection.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If the gate dielectric layer is removed to form work function layers, then different threshold voltages are achieved, but the fin structure is exposed to damage

Engineering Contradiction:

Improvework function layer formationVSAvoidetching damage to fin

Core Design Contradiction:

Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The sacrificial layer serves as a mediator that enables the removal of the gate dielectric layer while protecting the fin structure. By etching through the gate dielectric layer to expose the sacrificial layer, and then removing the sacrificial layer, the process achieves gate dielectric removal without direct exposure of the fin structure to harmful etchants.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial layer acts as a cushioning layer that absorbs the impact of etching processes. It is positioned between the gate dielectric layer and the fin structure, providing a buffer that prevents etching damage from reaching the fin structure while still allowing the necessary removal of the gate dielectric layer to form work function layers.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If multiple work function layers are formed, then device performance is optimized, but the manufacturing process becomes more complex

Engineering Contradiction:

ImproveFinFET performanceVSAvoidetching process steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The gate dielectric layer is segmented into different regions with different thicknesses or compositions, allowing for the formation of multiple work function layers with different threshold voltages. The sacrificial layer is also segmented to correspond with these different regions, enabling selective removal patterns that create the desired work function layer configuration without requiring excessively complex etching processes.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents damage to the fin structure during etching, allowing for the formation of various work function layers and achieving desired threshold voltages without compromising the FinFET performance.

Implementation Method 1

an anisotropic etching process changes an etching characteristic of the gate dielectric layer

Methodology Applied

Scientific EffectAnisotropic etching:

Implementation Method 2

the sacrificial layer and the gate dielectric layer are etched to expose the interfacial layer

Methodology Applied

Scientific EffectIsotropic etching:

Data Source

PatentUS20240186390A1Fin field-effect transistor and method of forming the same

Publication Date: 2024.06.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a gate dielectric layer disposed over the fin structure. The semiconductor device includes an interfacial layer over a top portion of the gate dielectric layer. A bottom portion of gate dielectric layer is free of contact with the interfacial layer. The semiconductor device includes a gate structure straddling the fin structure.