FinFET Gate Stack Etching for Uniform Threshold Voltage Tuning
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Solution Overview
Problem
In the manufacturing of field effect transistors, particularly FinFETs, the challenge lies in adjusting threshold voltage without damaging underlying layers, as existing methods for removing or thinning work function adjustment and barrier layers can cause damage to other FETs and result in non-uniform threshold voltages due to the complexity of forming gate stacks in narrow trenches.
Innovation Solution
A novel process involving the sequential removal of work function adjustment and barrier layers using wet etching operations, with specific etchants and annealing steps, to maintain layer integrity and achieve uniform threshold voltages across different FET types, including the use of conductive layers like TiN and TaN, and work function materials such as TiAl and TiAlC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If work function adjustment and barrier layers are removed or thinned to adjust threshold voltage, then threshold voltage can be adjusted, but underlying layers are damaged and other FETs are affected
Solution Approach 1:
The patent segments the gate stack into multiple distinct layers including work function adjustment layers and barrier layers with different material compositions. This segmentation allows selective removal or thinning of specific layers through targeted etching processes, enabling precise threshold voltage adjustment without damaging underlying layers or adjacent FET structures.
Solution Approach 2:
The patent introduces barrier layers as intermediary structures between the work function adjustment layers and the underlying channel region. These barrier layers protect the underlying layers during etching processes while still allowing the work function adjustment layers to be selectively removed or thinned to achieve the desired threshold voltage adjustment.
2Ease of manufacture
If complex processes are used to form gate stacks in narrow trenches, then gate stacks can be formed, but threshold voltages become non-uniform
Solution Approach 1:
The patent applies local quality by creating gate stacks with spatially varying material compositions and thicknesses. Different regions of the gate stack have different work function adjustment layer thicknesses or compositions, allowing local threshold voltage tuning while maintaining overall process simplicity and uniformity across the device array.
Solution Approach 2:
The patent utilizes parameter changes in the work function adjustment layers, such as varying material composition ratios or layer thicknesses, to achieve precise threshold voltage control. By changing these parameters in a controlled manner during deposition, uniform threshold voltages can be achieved across multiple FETs without requiring complex post-processing steps.
3Productivity
If multiple FET devices with varying threshold voltages are produced using the same process, then productivity increases, but process complexity increases
Solution Approach 1:
The patent implements universality by designing a single integrated process flow that can produce multiple FET device types with different threshold voltages using the same fabrication steps. The multi-layer gate stack structure with work function adjustment layers and barrier layers serves multiple functions: it enables threshold voltage adjustment, provides layer protection, and allows selective modification to create different device characteristics from the same base process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process allows for precise adjustment of threshold voltages while minimizing damage to underlying layers, enabling the production of multiple FET devices with varying threshold voltages using the same process, and preventing plasma damage to other FET regions.
Implementation Method 1
sequential removal of work function adjustment and barrier layers using wet etching operations
Implementation Method 2
annealing steps, to maintain layer integrity and achieve uniform threshold voltages
Data Source
AI summary
In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.