FinFET Gate Stack Etching for Multiple Threshold Voltages
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Solution Overview
Problem
Existing FinFET technologies face challenges in forming multiple threshold voltages without damaging the fin structure during etching processes, leading to leakage paths and performance issues.
Innovation Solution
A method involving the formation of a first interfacial layer over the fin structure, followed by a gate dielectric layer and a sacrificial layer, with anisotropic and isotropic etching processes to change the etching characteristics of the gate dielectric layer, allowing for the formation of different work function layers without damaging the fin structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional etching processes are used to form multiple threshold voltages, then different work function layers can be formed, but the fin structure is damaged and leakage paths are created
Solution Approach 1:
A sacrificial layer is introduced as an intermediary between the gate dielectric layer and the fin structure. This sacrificial layer is selectively removed through isotropic etching to expose portions of the gate dielectric layer, enabling formation of different work function layers at different locations without directly etching the fin structure, thus preventing damage and leakage paths while achieving multiple threshold voltages
Solution Approach 2:
The gate dielectric layer is formed over the fin structure before any etching or work function layer formation. This preliminary formation protects the fin structure from direct exposure to harsh etching conditions, and subsequent selective removal of gate dielectric layer portions allows for creating multiple threshold voltages without damaging the underlying fin structure
2Adaptability or versatility
If the gate dielectric layer is completely removed to form work function layers, then multiple threshold voltages are achieved, but the fin structure is exposed to damage
Solution Approach 1:
The gate dielectric layer is selectively removed only at specific locations where different work function layers are desired, rather than complete removal. This localized removal exposes only the necessary portions of the fin structure for creating multiple threshold voltages, while leaving other portions protected by the gate dielectric layer, thus achieving versatility without widespread damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of FinFET devices with multiple threshold voltages without damaging the fin structure, enhancing the overall performance by preventing leakage paths and maintaining the integrity of the fin structure.
Implementation Method 1
anisotropic etching processes to change the etching characteristics of the gate dielectric layer
Implementation Method 2
isotropic etching processes to change the etching characteristics of the gate dielectric layer
Data Source
AI summary
A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.