FinFET Gate Stack Integration for Short Channel Effect Control
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Solution Overview
Problem
The manufacturing of fully depleted fin field effect transistors is challenging due to the difficulty in achieving thin silicon channel layers with traditional bulk silicon-based processes, and existing 3D semiconductor devices face short channel effects that affect device performance and increase power consumption.
Innovation Solution
A method involving the integration of high-k gate dielectric and metal gate processes into fin field effect transistors, along with strained source/drain regions, is employed to reduce short channel effects and enhance device performance. This includes forming an SOI substrate, creating a basic fin structure, forming source/drain regions, and integrating a gate stack across the fin structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional bulk silicon-based processes are used to manufacture fully depleted devices, then manufacturing simplicity is maintained, but the ability to achieve thin silicon channel layers is insufficient
Solution Approach 1:
The patent transitions from planar 2D device architecture to 3D vertical FinFET structure. The channel region is formed as a vertical fin extending from the substrate, allowing the gate to wrap around three sides of the channel. This dimensional change enables precise control of channel thickness through fin height while maintaining manufacturability with modified standard processes.
Solution Approach 2:
The channel region is segmented into a distinct vertical fin structure separated from the bulk substrate by an isolation layer. This segmentation allows independent control and optimization of channel thickness without affecting the entire substrate, enabling thin channel layers to be manufactured using standard bulk silicon processes combined with selective etching and deposition techniques.
2Productivity
If channel length is shortened to improve device scaling, then device density increases, but short channel effects worsen
Solution Approach 1:
By transitioning to vertical FinFET architecture, the gate achieves three-sided control of the channel, providing superior electrostatic control compared to planar devices. This enhanced control allows significant reduction in channel length while maintaining effective suppression of short channel effects through the wrapped gate structure that controls the channel from multiple directions.
Solution Approach 2:
The patent employs high-k gate dielectric materials combined with metal gate electrodes to enhance gate control over the channel. The high-k material provides increased capacitance and improved electrostatic control, enabling better suppression of short channel effects at scaled dimensions while maintaining lower operating voltages and reduced leakage currents.
3Manufacturing precision
If conventional planar devices are used, then manufacturing is simpler, but fully depleted channel control is unachievable
Solution Approach 1:
The vertical FinFET structure provides natural channel isolation through the substrate interface, eliminating the need for complex fully depleted SOI substrate preparation. The channel is fully depleted through its entire thickness by design, achieved through the vertical fin geometry and gate wrapping, while maintaining compatibility with standard bulk silicon manufacturing processes.
4Reliability
If high-k gate dielectric and metal gate are integrated into FinFET, then short channel effects are reduced, but manufacturing process complexity increases
Solution Approach 1:
The gate dielectric and gate electrode structures are formed as integrated parts of the FinFET fabrication sequence, with the gate wrap-around structure being established during the fin formation process. The high-k dielectric is deposited conformally on the vertical fin surfaces, and metal gates are patterned to wrap around all three sides of the channel, achieving complete channel control through coordinated process steps.
Data Source
AI summary
The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure from an SOI layer; forming source/drain regions (110) on both sides of the basic fin structure; forming a fin structure between the source/drain regions (110) from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.