FinFET Gate Stack Passivation Through N-Type Work Function Metal
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices, such as FinFETs, continue to shrink in feature size, they face challenges with defects in gate dielectric layers that affect device performance and reliability, including dangling bonds and oxygen vacancies, which existing technologies struggle to address effectively without damaging the transistor.
Innovation Solution
A remote plasma process is used to introduce passivating species like fluorine or nitrogen radicals into the gate dielectric layers, which are facilitated by an n-type work function metal to improve conformity and doping concentration, and can be performed at low temperatures to minimize damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional passivation treatments are used on gate dielectric layers, then defects like dangling bonds and oxygen vacancies can be addressed, but the transistor may suffer from thermal damage
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature processes to low-temperature plasma treatment (below 200°C), enabling effective defect passivation without causing thermal damage to the transistor structure. This parameter change resolves the contradiction between achieving reliable defect fixation and avoiding thermal harm.
Solution Approach 2:
The patent replaces thermal-based passivation mechanisms with plasma-based chemical treatment. Instead of using heat to activate passivation reactions, the invention uses reactive species in plasma to chemically passivate defects at low temperatures, substituting a thermal system with a chemical plasma system that avoids thermal damage.
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but defects in gate dielectric layers become more prevalent
Solution Approach 1:
The patent applies preliminary passivation treatment to gate dielectric layers before subsequent processing steps. By pre-passivating defects in the gate dielectric at low temperature, the invention prepares the structure to maintain reliability even as feature sizes are reduced for higher integration density, addressing the contradiction between scaling and defect prevalence.
3Manufacturing precision
If high temperature processes are used for passivation treatment, then defect fixation may be more effective, but the risk of damaging the transistor increases
Solution Approach 1:
The patent fundamentally changes the temperature parameter from high temperature to low temperature (below 200°C) while maintaining effective defect fixation through plasma chemistry. This parameter change enables achieving manufacturing precision for defect fixation without incurring the harmful effect of transistor damage from excessive heat.
Solution Approach 2:
The patent introduces plasma as an intermediary medium to transfer passivation capability without requiring high temperature. The reactive species in plasma act as intermediaries that can chemically passivate defects at low temperatures, mediating between the need for effective defect fixation and the constraint of avoiding thermal damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively fixes defects in the gate dielectric layers, enhancing device performance and reliability by improving the film quality and reducing the risk of thermal damage during the passivation treatment.
Implementation Method 1
A remote plasma process is used to introduce passivating species like fluorine or nitrogen radicals into the gate dielectric layers
Implementation Method 2
introduce passivating species like fluorine or nitrogen radicals into the gate dielectric layers
Implementation Method 3
an n-type work function metal to improve conformity and doping concentration
Data Source
AI summary
A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.