FinFET Gate Stack Segmentation for Threshold Voltage Control
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Solution Overview
Problem
Semiconductor devices require transistors with varying threshold voltages and conductivity types to efficiently operate logic circuits, but existing manufacturing methods struggle to achieve the necessary precision and performance, particularly in forming fin-type transistors with high threshold voltages and low leakage currents.
Innovation Solution
The semiconductor device includes a substrate with an active fin and isolation layer, featuring a gate structure with a metal pattern of specific conductivity types directly contacting a gate insulation layer, and source/drain regions with different conductivity types, formed using a method that involves epitaxial growth and precise doping to create channel regions and transistors with targeted threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing methods are used to form transistors, then the manufacturing process is simple, but the threshold voltage precision and leakage current control are insufficient
Solution Approach 1:
The gate structure is segmented into multiple distinct layers: gate insulation layer, first metal layer (work function control), and second metal layer (threshold voltage adjustment). This segmentation allows independent optimization of each layer's function, achieving precise threshold voltage control while maintaining manufacturability through standardized layer-by-layer fabrication processes.
Solution Approach 2:
Different regions of the transistor are assigned different conductivity types: the gate structure and channel region use one conductivity type while source/drain regions use the opposite conductivity type. This local quality differentiation enables precise control of carrier flow and threshold voltage characteristics specific to each region's functional requirements.
2Reliability
If conventional transistor structures are used, then the device structure is simple, but leakage currents are high
Solution Approach 1:
The threshold voltage is precisely controlled by adjusting the composition and thickness parameters of the metal layers. By changing the work function parameters of the first metal layer and adding the second metal layer with specific electrical properties, the threshold voltage is optimized to minimize leakage currents while maintaining the transistor's switching functionality.
Solution Approach 2:
The gate structure employs a composite material system combining gate insulation material with multiple metal layers of different electrical properties. This composite structure integrates the insulating properties of the gate insulation layer with the conductive and work function properties of the metal layers, achieving low leakage currents through enhanced electrical isolation and controlled carrier injection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of transistors with higher threshold voltages and reduced leakage currents, suitable for serving as header or footer transistors in logic circuits, enhancing the semiconductor device's performance and integration density.
Implementation Method 1
the first metal pattern having a first conductivity type and directly contacting the first gate insulation layer pattern
Implementation Method 2
a first channel region at a portion of the active fin facing a bottom surface of the first gate structure, the first channel region including impurities having the first conductivity type
Implementation Method 3
the second source/drain regions of the second transistor may be formed in a semiconductor pattern formed by an epitaxial growth process
Data Source
AI summary
A semiconductor device includes a substrate including an active fin and an isolation layer thereon, a first gate structure on the active fin, the first gate structure including a first gate insulation layer pattern and a first metal pattern, and the first metal pattern having a first conductivity type and directly contacting the first gate insulation layer pattern, a first channel region at a portion of the active fin facing a bottom surface of the first gate structure, the first channel region including impurities having the first conductivity type, and first source/drain regions at upper portions of the active fin adjacent to opposite sidewalls of the first gate structure, the first source/drain regions including impurities having a second conductivity type different from the first conductivity type.