FinFET Gate Electrode Stress Control for Mobility
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Solution Overview
Problem
Semiconductor devices face challenges in optimizing charge carrier mobility due to varying responses to compressive and tensile stresses in n-FET and p-FET devices, requiring specific engineering and optimization to enhance performance at smaller dimensions.
Innovation Solution
A finFET structure with a gate electrode having intrinsic tensile stress of 500 to 1500 MPa is used, correlating with axially specific piezoresistance coefficients to optimize charge carrier mobility within the semiconductor fin channel region, enhancing both n-finFET and p-finFET performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate base materials are used as substrates for silicon epitaxial fin sidewall channel layer formation in complementary finFET devices, then complementary stress levels can be achieved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent applies parameter changes by controlling the intrinsic stress of the gate electrode material and adjusting its thickness to induce specific stress levels in the channel region. By changing the stress parameter of the gate electrode (from compressive to tensile) and its dimensional parameter (thickness), the patent achieves optimized charge carrier mobility without requiring separate base materials for n-FET and p-FET devices.
2Reliability
If n-FET and p-FET devices are engineered with specific stress optimizations, then charge carrier mobility is enhanced, but the manufacturing process becomes more complex due to different piezoresistance coefficients
Solution Approach 1:
The patent applies universality by using a single gate electrode structure that serves multiple functions: it provides electrical gating control and simultaneously induces mechanical stress in the channel region. This unified approach allows the same gate electrode to optimize both n-FET and p-FET devices on the same substrate, eliminating the need for separate stress engineering processes for different device types.
Solution Approach 2:
The patent changes the stress parameter of the gate electrode to induce complementary stress effects in n-FET and p-FET devices. By adjusting the gate electrode's intrinsic stress (tensile or compressive) and thickness, the patent achieves optimized charge carrier mobility for both device types using a unified fabrication approach.
3Productivity
If device dimensions are reduced for continued performance enhancement, then integration density increases, but optimizing stress effects becomes more difficult at smaller dimensions
Solution Approach 1:
The patent applies parameter changes by precisely controlling the gate electrode thickness and intrinsic stress to achieve optimal stress induction in the channel region. By adjusting these parameters, the patent maintains effective stress control even as device dimensions are reduced, enabling continued performance enhancement at smaller dimensions with improved integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significant charge carrier mobility enhancement, with n-finFETs experiencing 77% and p-finFETs experiencing 60% mobility improvement, respectively, through tailored stress induction within the semiconductor fin channel region.
Implementation Method 1
at least one semiconductor fin having a crystallographic orientation and an axially specific piezoresistance coefficient
Data Source
AI summary
A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.