FinFET Gate Structure Suppressing Short Channel Effect
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Solution Overview
Problem
Existing semiconductor devices face challenges in simultaneously suppressing the short channel effect and improving mobility, particularly in V-shaped MOSFET structures, due to difficulties in generating stress efficiently and restricted surface orientation combinations.
Innovation Solution
A semiconductor device with a gate electrode formed on a gate insulating film over a boundary between inclined semiconductor faces, where the source impurity region overlaps the gate within one face and the drain impurity region is directly under the other face, closer to the boundary, enhancing surface potential and shielding the drain electric field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length is shortened to improve integration density, then higher levels of integration are achieved, but the short channel effect appears and worsens
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional FinFET structure by forming fins perpendicular to the substrate surface. This dimensional change allows the gate to wrap around the channel in a T-shaped configuration, providing better electrostatic control over the channel and suppressing the short channel effect even at scaled dimensions.
Solution Approach 2:
The patent employs a composite material structure with a semiconductor layer having a different composition than the substrate, forming fins with specific crystal orientations. The FinFET structure combines multiple materials (semiconductor layer, gate electrode, gate insulating film) in a composite configuration that achieves both scaling and short channel effect suppression.
2Power
If the gate insulating film thickness is reduced to increase gate capacitance, then gate capacitance increases, but the film thickness reaches a physical limit below two nm
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate insulating film by using high-k materials such as hafnium oxide or hafnium nitride instead of traditional silicon dioxide. This parameter change allows achieving the required gate capacitance with a physically thicker film, avoiding the limitations of ultra-thin films below two nm.
3Power
If the impurity concentration of the channel region is increased to improve current drive, then current drive improves, but junction withstand voltage decreases due to Zener breakdown
Solution Approach 1:
The patent applies local quality by forming extension regions with graded impurity concentrations. The channel region maintains high impurity concentration for current drive, while the extension regions adjacent to the gate have lower impurity concentrations to prevent Zener breakdown, creating a spatially varying impurity profile that optimizes both current drive and breakdown voltage.
4Reliability
If the junction depth of source and drain diffusion layers is reduced to suppress short channel effect, then short channel effect is suppressed, but series resistance of source and drain increases
Solution Approach 1:
The patent resolves this contradiction by transitioning to a vertical FinFET structure where the channel extends in the depth direction perpendicular to the substrate. This allows shallow junctions at the surface to maintain short channel effect suppression while the vertical channel provides sufficient current drive through increased effective channel width and optimized impurity profiling along the fin height.
5Power
If a V-shaped MOSFET structure is used to improve performance, then mobility improvement is achieved, but stress generation becomes difficult and surface orientation combinations are restricted
Solution Approach 1:
The patent uses a composite material structure with a semiconductor layer having a different composition than the substrate to form the FinFET fins. This composite structure enables controlled stress generation through lattice mismatch between layers, providing mobility enhancement without requiring V-shaped geometries or specific surface orientations, thus simplifying manufacturing.
Data Source
AI summary
A semiconductor device including: a semiconductor region having a first semiconductor face and a second semiconductor face connected to the first semiconductor face and having an inclination with respect to the first semiconductor face; a gate insulating film formed on the first and on the second semiconductor faces; a gate electrode formed on the gate insulating film including a part on a boundary between the first semiconductor face and the second semiconductor face; a source impurity region formed in the semiconductor region so as to overlap the gate electrode within the first semiconductor face with the gate insulating film interposed between the source impurity region and the gate electrode; and a drain impurity region formed in the semiconductor region directly under the second semiconductor face at least.