FinFET Gate Tapering and Fill Structure to Prevent Metal Gate Voids
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Solution Overview
Problem
In the semiconductor industry, the formation of Fin Field-Effect Transistor (FinFET) devices faces challenges due to the difficulty in depositing material between shrinking fin features, leading to voids and defects in the gate electrode and subsequent metal gate structure.
Innovation Solution
The method involves forming a dummy gate over a fin, thinning the lower portion of the dummy gate near isolation regions, and depositing a gate fill material along the thinned dummy gate. This is followed by forming gate spacers and replacing the dummy gate with a metal gate, ensuring that any voids are filled and removed in the subsequent processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If material is deposited between shrinking fin features, then integration density is improved, but voids and defects occur in the gate electrode structure
Solution Approach 1:
The gate structure is divided into multiple segments: a tapered dummy gate portion, a gate fill material portion, and a metal gate portion. This segmentation allows each part to serve a specific function - the tapered dummy gate facilitates material deposition, the gate fill material fills voids, and the metal gate provides final functionality, thereby resolving the contradiction between high integration density and structural quality
Solution Approach 2:
The dummy gate structure with a tapered bottom portion is formed in advance before the gate fill material is deposited. This preliminary action creates a geometry that facilitates complete material deposition and eliminates voids in the gate electrode, ensuring high manufacturing precision while maintaining the ability to achieve high integration density
2Ease of manufacture
If a standard dummy gate is formed, then the fabrication process is simplified, but voids and defects remain in the gate electrode structure
Solution Approach 1:
The dummy gate is designed with non-uniform local quality - the bottom portion has a tapered geometry with gradually decreasing thickness, while the upper portion maintains standard dimensions. This local variation in geometry specifically addresses the void formation problem at the bottom of the gate electrode without complicating the overall fabrication process
3Area of stationary object
If the gate structure is positioned closer to source/drain regions, then device size is reduced, but leakage current increases
Solution Approach 1:
The gate fill material acts as an intermediary between the dummy gate structure and the metal gate, and also serves as a spacer that maintains an optimal distance between the gate structure and source/drain regions. This intermediary element allows the device to be compact while preventing direct contact that would cause leakage current
Data Source
AI summary
A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.