FinFET Metal Gate Structure for Vt Uniformity and Gate Protection
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Solution Overview
Problem
Existing FinFET devices and methods for forming them have limitations in achieving optimal performance and reliability due to challenges in processing and manufacturing, particularly in achieving uniform threshold voltage and effective gate control.
Innovation Solution
The method involves forming a FinFET device with a metal gate strip having a reversed T-shaped profile, with voids in the bottom portion, and utilizing thicker upper gate spacers and a dielectric helmet to enhance protection and control, thereby improving device performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional planar transistor is used, then the fabrication process is simpler, but the functional density and performance are limited
Solution Approach 1:
The patent transitions from a planar two-dimensional transistor structure to a three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change increases the effective channel area and gate control without increasing the planar footprint, thereby improving functional density while managing the complexity through a well-defined vertical architecture.
2Speed
If the gate strip is made thinner to reduce capacitance, then the switching speed improves, but the gate control and reliability deteriorate
Solution Approach 1:
The gate strip is extended into the third dimension by forming vertical fins that protrude from the substrate. This allows the gate to control a larger channel area with the same planar footprint, improving both switching speed and gate control effectiveness simultaneously by increasing the effective surface area without increasing the lateral dimensions.
Solution Approach 2:
The gate strip is positioned within a multi-layer structure that includes interfacial layers, dielectric layers, and metal layers. This nested arrangement allows the gate to be integrated into a complex three-dimensional structure that provides both electrical control and mechanical support, enhancing reliability while maintaining fast switching performance.
3Ease of manufacture
If the fabrication process is simplified, then the manufacturing cost decreases, but the manufacturing precision and uniformity of threshold voltage worsen
Solution Approach 1:
Interfacial layers are formed on the substrate before the gate strip is deposited. This preliminary action prepares the surface with controlled electrical and mechanical properties, ensuring uniform threshold voltage across the device while maintaining a streamlined fabrication process that doesn't require additional complex steps later.
Solution Approach 2:
The device structure incorporates multiple materials including semiconductor substrate, dielectric materials, metal gate materials, and interfacial layers. This composite structure allows each material to be optimized for its specific function while being integrated through standard fabrication processes, achieving both manufacturing precision and ease of manufacture.
4Adaptability or versatility
If the gate strip extends over isolation strips, then the device integration improves, but the metal gate damage and reliability issues increase
Solution Approach 1:
The gate strip is extracted from the regions overlying the isolation strips, creating a configuration where the gate terminates before reaching the isolation structures. This prevents direct contact between the metal gate and isolation materials that could cause damage or reliability issues, while the gate still effectively controls the channel region.
Solution Approach 2:
Dielectric layers and interfacial layers are introduced as intermediary structures between the gate strip and the isolation strips. These intermediary layers provide electrical isolation and mechanical protection, allowing the gate to be integrated with the surrounding device structures without direct exposure to potentially damaging isolation materials.
Data Source
AI summary
Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.