FinFET Gate WFM Structure for Multiple Threshold Voltages
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Solution Overview
Problem
As IC technologies shrink, the challenge of stacking work function metal (WFM) layers in FinFET devices becomes significant due to decreased fin-to-fin pitches, leading to limitations in achieving multiple threshold voltages without WFM layers merging.
Innovation Solution
A WFM structure is implemented with a thinner p-type WFM portion and a thicker n-type WFM portion, where the p-type WFM portion is formed by patterning an n-type WFM layer directly on a high-k dielectric layer without an intermediate cap, and a glue metal layer serves as both the p-type WFM and an additional layer, allowing for high or low work functions without the need for multiple layers, thereby reducing overall thickness and enabling multiple threshold voltages in FinFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple WFM layers are stacked to achieve multiple threshold voltages, then device performance is improved, but fin-to-fin pitch increases and manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by forming different thicknesses of WFM layers in different regions. Specifically, a first WFM layer is formed with a first thickness over a first fin and a second WFM layer is formed with a second thickness over a second fin, allowing each fin to have locally optimized work function and threshold voltage characteristics without requiring multiple stacked layers across all fins.
Solution Approach 2:
The patent segments the WFM layer formation process into separate sequential steps rather than stacking multiple complete layers. The first WFM layer is formed and patterned, then the second WFM layer is formed with different thickness characteristics, allowing independent control of WFM thickness for different fins without the complexity of stacking and patterning multiple complete layers.
2Adaptability or versatility
If multiple WFM layers are stacked to achieve multiple threshold voltages, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the WFM layer formation into sequential deposition and patterning steps rather than stacking complete layers. This allows simpler manufacturing by forming the first WFM layer, patterning it, then forming the second WFM layer with different thickness characteristics, avoiding the complexity of aligning and patterning multiple stacked layers.
Solution Approach 2:
The patent changes the thickness parameter of WFM layers formed at different stages. The first WFM layer is formed with a first thickness and the second WFM layer is formed with a second thickness that is less than the first thickness, allowing control of work function and threshold voltage through parameter variation rather than through multiple stacked layers.
3Length of stationary object
If thinner WFM structure is used, then fin-to-fin pitch is reduced, but achieving multiple threshold voltages becomes difficult
Solution Approach 1:
The patent achieves multiple threshold voltages with reduced fin-to-fin pitch by applying local quality - different fins have different WFM layer thicknesses. The first fin has a first WFM layer with first thickness providing first work function, while the second fin has a second WFM layer with second thickness providing second work function, enabling multiple threshold voltages without requiring thick stacked WFM layers.
Solution Approach 2:
The patent segments the WFM structure into multiple sequentially formed layers with different thickness characteristics, allowing each fin to receive the appropriate WFM thickness for its desired threshold voltage. This segmented approach enables multiple threshold voltages to be achieved with overall reduced WFM structure thickness compared to stacking multiple complete layers.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.