FinFET Gate Width Variation via Sidewall Spacer Etching
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Solution Overview
Problem
Current methods for fabricating FinFET structures struggle with high channel length variability and static current leakage, particularly at smaller channel lengths, as they do not allow for the formation of gate structures with different widths, which is crucial for optimizing transistor performance and reducing leakage.
Innovation Solution
The method involves forming a hard mask layer and depositing a sidewall spacer material layer over mandrels on a gate-forming material layer, where the spacer layer is etched to create spacers of varying thicknesses, allowing for the fabrication of gate structures with different widths and channel lengths by using these spacers as etch masks during the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current fabrication methods are used to create small channel length FinFETs, then higher current drive strength and operating frequency are achieved, but static current leakage increases and channel length variability increases
Solution Approach 1:
The patent applies local quality by creating different gate widths (and thus different channel lengths) in different regions of the semiconductor device. By forming sidewall spacers of varying thicknesses in different areas, the invention enables some transistors to have shorter channels for high performance while others have longer channels for low leakage, allowing each region to be optimized for its specific function.
Solution Approach 2:
The invention segments the gate structure into different width regions by forming sidewall spacers with different thicknesses. This segmentation allows the semiconductor device to contain multiple transistor types (different channel lengths) within the same device structure, enabling simultaneous optimization for both speed and power consumption in different functional blocks.
2Object-generated harmful factors
If gate structures with different widths are formed to reduce leakage, then static current leakage decreases, but manufacturing complexity increases due to additional process steps
Solution Approach 1:
The patent applies preliminary action by forming all sidewall spacers of different thicknesses simultaneously in a single deposition process before the gate etching step. This preliminary formation of varied spacer thicknesses allows subsequent single-step gate etching to produce different gate widths, avoiding the need for multiple separate masking and etching processes that would otherwise be required.
Solution Approach 2:
The invention changes the physical parameter of spacer thickness to control gate width. By depositing sidewall spacer material to different thicknesses in different regions (using techniques such as selective deposition or varying deposition conditions), the patent directly controls the final gate width without requiring different masking layers or multiple etching steps, thus simplifying the overall fabrication process.
3Ease of manufacture
If uniform gate widths are used throughout the device, then fabrication process is simpler, but all transistors cannot be optimized for different functions requiring different channel lengths
Solution Approach 1:
The patent achieves universality by creating a single fabrication process that produces multiple transistor types within the same device. The sidewall spacer formation process, combined with a single gate etching step, simultaneously creates transistors with different channel lengths suited for different functions (e.g., critical timing paths vs. non-critical paths), allowing one process to serve multiple optimization goals.
Solution Approach 2:
The invention introduces dimensional variation in the gate width (lateral dimension) by controlling sidewall spacer thickness. This dimensional change allows the same fabrication process to produce gates of different widths, enabling functional optimization across different transistor regions without adding process complexity, effectively using geometric variation to achieve functional diversity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces variability in minimum channel lengths, improves gate structure alignment, and enables the simultaneous fabrication of both small and large-width gate structures, thereby decreasing static leakage and power consumption in semiconductor devices.
Implementation Method 1
A sidewall spacer material layer is deposited overlying the plurality of mandrels
Implementation Method 2
The sidewall spacer material layer overlying the first portion of the gate-forming material layer is partially etched
Data Source
AI summary
Methods for fabricating a FinFET structure are provided. One method comprises forming a hard mask layer on a gate-forming material layer having a first portion and a second portion. A plurality of mandrels are fabricated on the hard mask layer and overlying the first portion and the second portion of the gate-forming material layer. A sidewall spacer material layer is deposited overlying the plurality of mandrels. The sidewall spacer material layer overlying the first portion of the gate-forming material layer is partially etched. Sidewall spacers are fabricated from the sidewall spacer material layer, the sidewall spacers being adjacent sidewalls of the plurality of mandrels. The plurality of mandrels are removed, the hard mask layer is etched using the sidewall spacers as an etch mask, and the gate-forming material layer is etched using the etched hard mask layer as an etch mask.