FinFET Gate Width Control via Single Etch SIT Process
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Solution Overview
Problem
Conventional FinFET fabrication processes require multiple etching steps, leading to poor gate width control and significant variation across the semiconductor substrate.
Innovation Solution
A single etching process is used to define the gate width of FinFETs through a modified sidewall image transfer (SIT) process, where an insulating spacer is replaced by a gate conductor, and a high-density bottom-up oxide fill is employed to isolate the gate from the substrate, reducing gate width variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple etching steps are used in conventional FinFET fabrication, then the process can be completed with standard lithographic tools, but gate width control deteriorates and significant variation occurs across the substrate
Solution Approach 1:
The patent combines multiple etching steps into a single etching process by using a spacer-formed mask that defines the gate width directly. The spacer is formed on the sidewall of the semiconductor fin, and a single anisotropic etch transfers this spacer-defined pattern to the gate region, eliminating the need for separate lithographic etching steps and achieving improved gate width control across the substrate.
Solution Approach 2:
The patent introduces a spacer as an intermediary element that mediates between the semiconductor fin and the gate structure. The spacer is formed on the sidewall of the fin and serves as a self-aligned mask that directly defines the gate width during the etching process, providing precise control without requiring additional lithographic steps.
2Manufacturing precision
If optical or ebeam lithography with trimming is used to form Fins, then the structure can be defined with good resolution, but the process complexity increases and gate width control deteriorates
Solution Approach 1:
The patent employs a self-aligned spacer formation process where the spacer is deposited conformally on the sidewall of the semiconductor fin and then anisotropically etched back. This self-aligned approach automatically defines the gate width based on the fin dimensions and spacer thickness, eliminating the need for separate lithographic trimming steps and reducing process complexity while maintaining precision.
Solution Approach 2:
The patent transitions from planar lithographic definition to three-dimensional spacer-based definition. Instead of defining gate width in the planar lithographic layer, the gate width is defined by the vertical spacer thickness on the fin sidewall, which is controlled by deposition thickness rather than lithographic resolution, thereby improving precision and simplifying the process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method provides improved gate width control and reduced variation across the substrate, enhancing gate-to-source/drain control while maintaining low gate-to-gate capacitance.
Implementation Method 1
growing an oxide on exposed surfaces of said semiconductor substrate, including portions of said pedestal regions
Data Source
AI summary
A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.