Fin FET Gate Line Width Adjustment for Stress Mitigation
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Solution Overview
Problem
Conventional fin FETs with polysilicon gates face issues with circuit shorts due to unbalanced stress caused by discontinuous regions, leading to distortion and failure in high-density electronic circuits.
Innovation Solution
The electronic circuit employs gate lines with a reduced line width in regions adjacent to slots, mitigating unbalanced stress from inter-dielectric layers like oxide, thereby preventing circuit shorts by adjusting the line width to reduce distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon gate lines with uniform width are used in fin FET arrays, then manufacturing simplicity is maintained, but unbalanced stress from discontinuous regions causes gate line distortion and circuit shorts
Solution Approach 1:
The gate line width is locally adjusted in specific regions adjacent to discontinuous regions (slots) where oxide deposition creates unbalanced stress. By making the gate line narrower in these critical areas, the stress-induced distortion is compensated, preventing circuit shorts while maintaining uniform width in other regions for manufacturing simplicity.
2Reliability
If gate line width is reduced in regions adjacent to slots, then stress-induced distortion is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The gate line width parameter is changed from a constant value to a spatially varying parameter. The line width is reduced only in specific regions adjacent to discontinuous regions where unbalanced stress occurs, while maintaining the original width in other regions. This targeted parameter modification balances the stress distribution without requiring complex manufacturing processes throughout the entire gate line.
Data Source
AI summary
An electronic circuit includes a plurality of fin lines on a substrate and a plurality of gate lines with a first line width, crossing over the fin lines. The gate lines are parallel and have a plurality of discontinuous regions forming as a plurality of slots. A region of any one of the gate lines adjacent to an unbalance of the slots has a second line width smaller than the first line width.