FinFET Gate Width Asymmetry for Threshold Voltage Control
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Solution Overview
Problem
As transistors become highly integrated, it is challenging to maintain a desired threshold voltage due to the reduction in sizes of gate electrodes and channels, necessitating new methods to achieve optimal performance.
Innovation Solution
A semiconductor device design featuring first and second active fins on a substrate with isolation patterns and gate structures, where the width of the gate structure overlapping the active fin is adjusted to achieve a desired threshold voltage for NMOS and PMOS transistors, with the width of the gate structure on the first active fin being greater than that on the second active fin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of gate electrodes and channels is reduced to achieve high integration, then device integration density is improved, but threshold voltage control becomes difficult
Solution Approach 1:
The patent applies local quality by making the gate structure width vary at different locations. Specifically, the gate structure has a first width at the first active fin and a second width at the second active fin, with different widths tailored to different transistor types (NMOS and PMOS). This allows each region to have optimized gate dimensions for its specific function, enabling precise threshold voltage control despite overall size reduction for high integration.
Solution Approach 2:
The patent employs asymmetry by designing non-uniform gate structure widths across different active fins. The gate structure intentionally has asymmetric dimensions where the width over the first active fin differs from the width over the second active fin. This asymmetric design enables differentiated threshold voltage control for NMOS and PMOS transistors, solving the threshold voltage control problem while maintaining high integration density.
2Manufacturing precision
If the gate structure width is increased to improve threshold voltage control, then threshold voltage precision is improved, but device area increases
Solution Approach 1:
The gate structure implements local quality by having different widths at different locations rather than a uniform width. The first width and second width are locally optimized for their respective active fins, allowing threshold voltage precision to be improved only where needed while avoiding unnecessary area increase across the entire device. This localized approach resolves the contradiction between precision and area.
Data Source
AI summary
A semiconductor device includes first and second active fins on first and second regions of a substrate, an isolation pattern on a boundary between the first and second regions and portions of the first and second regions adjacent thereto and separating the first and second active fins, a first gate structure on the first active fin and the isolation pattern on the first region, a second gate structure on the second active fin and the isolation pattern on the second region, a first source/drain layer on the first active fin adjacent to the first gate structure, and a second source/drain layer on the second active fin adjacent to the second gate structure. A width of a portion of the first gate structure overlapping the first active fin is greater than that of a portion of the second gate structure overlapping the second active fin.