FinFET Gate-Wrapped Source and Drain for PCM Leakage
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Solution Overview
Problem
Moderate doping of FinFET source and drain regions in phase change memory (PCM) technologies leads to high parasitic resistance, degrading access transistor drive current due to increased susceptibility to leakage currents in nanometer scaled access transistor configurations.
Innovation Solution
A FinFET device structure where the gate region is wrapped around moderately doped source and drain regions, reducing series resistance and leakage currents by inducing additional electrons and holes when the metal gate is turned on, and maintaining low resistance when turned off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If moderate doping of FinFET source and drain regions is used to suppress leakage current, then off-state leakage is reduced, but parasitic resistance increases degrading drive current
Solution Approach 1:
The gate region is extended from a planar configuration to wrap around the source and drain regions in three dimensions. This gate-wrapping structure provides additional control over the channel and reduces parasitic resistance by establishing electrical contact with multiple sides of the source and drain regions, thereby improving drive current while maintaining moderate doping levels for leakage suppression.
Solution Approach 2:
The gate region is positioned to surround and wrap around the source and drain regions, creating a nested configuration where the gate envelops portions of the doped regions. This nested structure allows the gate to control carrier flow from multiple directions and reduce series resistance without requiring heavy doping.
2Quantity of substance
If nanometer scaled access transistor configurations are used for high density PCM, then memory density is improved, but susceptibility to leakage currents increases
Solution Approach 1:
The FinFET structure utilizes vertical fins extending from the substrate, transforming the traditional planar transistor into a three-dimensional configuration. This vertical scaling enables higher memory density while the gate-wrapping structure provides enhanced control over the short channel, suppressing leakage currents through improved electrostatic control from multiple gate contacts.
Solution Approach 2:
The gate region is segmented into multiple sections that wrap around different sides of the channel and doped regions. This segmentation allows independent optimization of each gate section to control leakage at different locations along the channel, addressing the increased leakage susceptibility inherent in scaled nanometer devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves drive current by two times or more while effectively suppressing off-state leakage currents, enhancing the performance of access transistors in high-density PCM applications.
Implementation Method 1
reducing series resistance and leakage currents by inducing additional electrons and holes when the metal gate is turned on
Implementation Method 2
maintaining low resistance when turned off
Data Source
AI summary
Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region.