Dual-Channel FinFET Fin Formation With Germanium Diffusion Control
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Solution Overview
Problem
Existing FinFET devices face challenges in controlling fin widths and profiles due to different etching rates between silicon and silicon germanium, leading to performance degradation and requiring additional protective liners, which complicates manufacturing and affects device reliability.
Innovation Solution
A method involving the formation of a transforming layer with germanium-based semiconductor material on silicon fins, followed by annealing to drive the material into the fins, allowing for adjustable germanium concentration and distribution, and subsequent gate strip formation, eliminates the need for conventional fin liners and improves fin control and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fin liners are used to protect silicon fins during manufacturing, then fin protection is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent removes the fin liner layer from the manufacturing process entirely. Instead of adding a protective liner and then removing it later, the process directly forms the gate dielectric layer over the fin structure, eliminating the unnecessary intermediate step and reducing overall process complexity while maintaining fin protection through self-aligned processes
Solution Approach 2:
The gate dielectric layer is formed in advance before fin trimming operations. This preliminary formation allows the dielectric layer to serve as a protective barrier during subsequent etching processes, eliminating the need for separate fin liner protection steps while maintaining chronological process efficiency
2Productivity
If different etching rates between silicon and silicon germanium are utilized, then selective material removal is improved, but fin width control precision deteriorates
Solution Approach 1:
The patent applies different etching conditions to different regions of the fin structure. By controlling etch selectivity and using self-aligned processes, the method achieves selective material removal at specific locations (such as spacer regions) while maintaining precise fin width control in the active device regions, allowing localized optimization without compromising overall precision
Solution Approach 2:
The patent utilizes changes in etching parameters (such as etch chemistry, temperature, and power) to selectively remove silicon germanium spacer material while preserving the silicon fin width. By adjusting etch selectivity ratios and process conditions, the method achieves both high productivity in spacer removal and precise fin width control through parameter optimization
3Reliability
If germanium concentration is increased for better voltage tuning, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The germanium-containing spacer material is formed in advance as part of the self-aligned process sequence. This preliminary formation establishes the germanium concentration profile before final fin trimming, allowing voltage tuning characteristics to be set early in the process while simplifying subsequent manufacturing steps by eliminating the need for separate germanium deposition and patterning operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient manufacturing of dual-channel FinFET devices with controlled silicon and silicon germanium fin shapes and sizes, enhancing performance and reliability by eliminating the need for protective liners and improving germanium concentration and distribution for better voltage tuning.
Implementation Method 1
annealing to drive the material into the fins
Data Source
AI summary
Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.