FinFET Gate-Adjacent Glue Layer for Leakage Isolation
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating reliable three-dimensional fin field effect transistors (FinFETs) due to decreasing feature sizes, which complicates the processing and manufacturing of these devices, particularly in reducing leakage and improving current flow.
Innovation Solution
A semiconductor structure is formed using a gate-replacement process involving the formation of fins on a substrate, followed by the deposition of gate spacers, source/drain structures, and a dielectric layer, with additional barrier layers and fluorine-doped layers to enhance insulation and reduce leakage, allowing for improved fabrication of FinFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes continue to decrease to increase functional density, then the number of interconnected devices per chip area increases, but fabrication processes become more difficult and reliability decreases
Solution Approach 1:
The patent transitions from planar device structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change increases functional density by utilizing the vertical dimension for the channel, allowing more devices to be packed into the same chip area while maintaining fabrication reliability through the self-aligned nature of the fin formation process
Solution Approach 2:
The gate structure is segmented into multiple components including gate spacers, metal gate layers, and dielectric layers formed at different stages. This segmentation allows each component to be optimized independently for its specific function, improving overall device reliability while enabling higher functional density through precise control of each segment's properties
2Ease of manufacture
If conventional planar MOSFET structures are used, then fabrication is simpler, but short channel effect increases and leakage current worsens
Solution Approach 1:
The patent employs vertical fins extending from the substrate to create a three-dimensional channel structure. This dimensional change provides better gate control over the channel from multiple sides, reducing the short channel effect and leakage current while maintaining fabrication simplicity through self-aligned processes
Solution Approach 2:
The device structure combines multiple materials including semiconductor fins, dielectric layers, metal gates, and source/drain structures. This composite structure allows optimization of each material's properties to reduce leakage current while maintaining ease of manufacture through established fabrication techniques
3Reliability
If FinFET structures are formed to reduce leakage and improve current flow, then device performance improves, but fabrication complexity increases
Solution Approach 1:
The patent forms gate spacers and defines fin regions before forming the metal gate and source/drain structures. This preliminary action establishes a self-aligned framework that simplifies subsequent fabrication steps, reducing overall fabrication complexity while achieving the desired FinFET performance
Solution Approach 2:
Dielectric layers are used as intermediary structures between the source/drain regions and metal gate, and between adjacent fins. These intermediary layers provide electrical isolation and structural support, enabling complex FinFET performance characteristics while managing fabrication complexity through standardized deposition and patterning processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described process enables the formation of FinFETs with reduced leakage and improved current flow by providing better insulation between source/drain and metal gate structures, enhancing parameters such as off-state current and breakdown voltage.
Implementation Method 1
barrier layer over the source/drain structure... providing better insulation between source/drain and metal gate structures
Implementation Method 2
additional barrier layers and fluorine-doped layers to enhance insulation and reduce leakage
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a gate structure, a source/drain structure, a barrier layer, and a glue layer. The gate structure is over a fin structure. The source/drain structure is in the fin structure and adjacent to the gate structure. The barrier layer is over the source/drain structure. The glue layer is adjacent to the barrier layer. The glue layer has an extending portion in direct contact with the gate structure.