FinFET Gradient Channel Germanium Silicon Ratio
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Solution Overview
Problem
Current FinFET fabrication processes face challenges in improving carrier mobility and overall device performance due to the architecture of the fin-shaped structure, which affects the channel region and overall performance of the semiconductor device.
Innovation Solution
A method for fabricating semiconductor devices involves forming fin-shaped structures on a substrate with shallow trench isolation, a gate structure, and source and drain regions of different conductive types, where the fin-shaped structure under the gate includes a first epitaxial layer, and the ratio of germanium to silicon is adjusted to form a gradient channel, suppressing ambipolar issues and enhancing driving current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FinFET fabrication processes are used, then the basic device structure is formed, but carrier mobility and device performance are limited due to the standard fin-shaped structure architecture
Solution Approach 1:
The patent applies local quality by forming a gradient channel structure where the germanium to silicon ratio varies spatially within the channel region. This creates different material compositions at different locations (higher Ge content near source, lower near drain), optimizing carrier mobility locally while managing ambipolar effects, thus improving device performance without fundamentally changing the overall FinFET architecture
Solution Approach 2:
The patent changes the compositional parameter of the channel material by adjusting the germanium to silicon ratio throughout the channel. This parameter change enables suppression of ambipolar issues and enhancement of driving current, resolving the performance limitations of conventional FinFETs while maintaining structural feasibility
2Manufacturing precision
If the fin-shaped structure architecture is used to increase gate overlap area, then channel control is improved, but ambipolar issues and limited carrier mobility occur
Solution Approach 1:
By implementing a gradient channel with spatially varying germanium content, the patent optimizes carrier mobility in specific regions of the channel. The higher germanium content near the source region enhances carrier injection, while the gradient profile suppresses ambipolar conduction, thereby improving reliability without compromising the gate control provided by the FinFET structure
Solution Approach 2:
The patent uses composite materials by combining silicon and germanium in varying ratios to form the channel structure. This composite approach leverages the beneficial properties of both materials: silicon provides stable crystal structure and good gate control, while germanium enhances carrier mobility and suppresses ambipolar effects, achieving improved reliability while maintaining manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility and device performance by reducing ambipolar issues and increasing driving current through the adjustment of the germanium to silicon ratio in the source, channel, and drain regions, effectively addressing the limitations of existing FinFET fabrication processes.
Implementation Method 1
forming a gate structure on the fin-shaped structure and the STI, in which the fin-shaped structure directly under the gate structure includes a first epitaxial layer
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a gate structure on the fin-shaped structure and the STI and the fin-shaped structure directly under the gate structure includes a first epitaxial layer; forming a source region having first conductive type adjacent to one side of the gate structure; and forming a first drain region having a second conductive type adjacent to another side of the gate structure.