FinFET Standard Cell Layout With Grid-Aligned Buried Power Rails
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Solution Overview
Problem
Buried power rails in semiconductor integrated circuits face challenges in providing sufficient current supply to transistors while maintaining regular placement of fin FETs, as they cannot be formed in regions with transistor sources, drains, and channels, and manufacturing variations restrict transistor size and placement.
Innovation Solution
The semiconductor integrated circuit device incorporates standard cells with fin FETs, where buried power lines are aligned along virtual grid lines, allowing for larger power lines without obstructing fin FET placement, ensuring sufficient current supply by positioning the center of the buried power lines on virtual grid lines or between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If buried power rails are made larger in width to provide sufficient current supply capability, then current supply capability is improved, but regular placement of fin FETs is blocked
Solution Approach 1:
The patent introduces virtual grid lines as a reference framework to resolve the spatial conflict between wide buried power rails and fin FET placement. By aligning power rail centers with virtual grid lines (which are equally spaced in the second direction), the design enables regular fin FET placement while maintaining sufficient power rail width for current supply.
2Reliability
If buried power rails are positioned to avoid transistor sources, drains, and channels, then manufacturing variations are prevented, but current supply capability is reduced
Solution Approach 1:
The patent applies local quality by making buried power rails larger in size specifically in the second direction (width) for standard cells that require higher current supply. This localized adaptation allows each standard cell to have power rail dimensions optimized for its specific current requirements while maintaining proper alignment with virtual grid lines to avoid transistor regions.
3Manufacturing precision
If fin FETs are restricted in size and placement positions to prevent manufacturing variations, then manufacturing precision is improved, but design flexibility is reduced
Solution Approach 1:
The patent creates a universal placement framework using virtual grid lines that can accommodate different fin FET sizes and standard cell configurations. The virtual grid lines serve as a common reference system that maintains manufacturing precision while allowing flexible design of various standard cells with different power rail dimensions and transistor arrangements.
Data Source
AI summary
A semiconductor integrated circuit device includes a plurality of cells each having a fin FET. A plurality of fins constituting the fin FET extend in the X direction and are placed on virtual grid lines equally spaced in the Y direction. The cells include buried power lines: cells larges in size in the Y direction include buried power lines larger in width. The center position of each of the buried power lines in the Y direction is on a virtual grid line or at a center position between adjacent virtual grid lines.