FinFET Metal Gate Formation Using a Hanging Dummy Gate

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Solution Overview

Problem

In the semiconductor industry, the formation of FinFET devices faces challenges such as voids in the gate electrode layer, leading to defects and increased resistance in the metal gate structure due to shrinking feature sizes and difficulties in depositing material between closely spaced fins, which can result in incomplete coverage and voids, affecting the integrity and performance of the device.

Innovation Solution

The method involves forming a hanging dummy gate structure with a gate fill material that fills the gap between the dummy gate and isolation regions, reducing the risk of voids and allowing for a subsequent replacement with a metal gate, which includes forming a dielectric layer over the dummy gate, etching to create a gap, depositing gate fill material, and then replacing the dummy gate and fill material with a metal gate structure through controlled etching processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If material is deposited between closely spaced fins to form gate electrode, then gate coverage is improved, but voids and defects occur due to incomplete coverage

Engineering Contradiction:
Improvegate electrode coverageVSAvoiddevice performance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A gate fill material is introduced as an intermediary substance between the dummy gate electrode and the isolation region. This gate fill material fills the gap and prevents void formation, serving as a mediator that resolves the coverage issue without requiring direct deposition between closely spaced fins

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate fill material is deposited before the metal gate structure is formed. This preliminary action ensures that the gap is filled and voids are prevented before the critical metal gate deposition step, improving subsequent manufacturing yield

Inventive Principle:
Principle #10Preliminary action

2Productivity

If feature size is reduced to increase integration density, then more components fit in given area, but voids and defects increase in gate electrode layer

Engineering Contradiction:
Improveintegration densityVSAvoidgate electrode integrity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The gate fill material serves as a mediator that enables continued scaling to smaller feature sizes by preventing void formation that would otherwise occur at reduced dimensions. This allows integration density to increase while maintaining gate electrode integrity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

By preliminarily filling the gap with gate fill material before metal gate deposition, the method enables reliable manufacturing at smaller feature sizes where direct deposition would fail due to void formation

Inventive Principle:
Principle #10Preliminary action

3Reliability

If dummy gate electrode is removed and replaced with metal gate, then device performance is improved, but voids and defects from previous steps are transferred to metal gate structure

Engineering Contradiction:
Improvedevice performanceVSAvoidmetal gate structure integrity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The gate fill material acts as a protective intermediary that prevents void formation during the dummy gate removal and metal gate formation steps. By maintaining continuous material presence in the gap, it ensures the metal gate structure inherits no voids or defects from previous processing steps

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the likelihood of defects and high resistance in the metal gate structure by ensuring complete coverage and reduces leakage current by increasing the distance between the metal gate and source/drain regions, thereby enhancing the overall performance and reliability of FinFET devices.

Implementation Method 1

forming a dielectric layer over the dummy gate

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

depositing gate fill material

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

etching to create a gap

Methodology Applied
Scientific EffectChemical Etching:

Data Source

PatentUS11908920B2Fin field-effect transistor device and method of forming the same
Publication Date: 2024.02.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11908920B2 patent drawing
  • US11908920B2 patent drawing
  • US11908920B2 patent drawing

AI summary

A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.