FinFET Hard Mask Capping to Prevent Etch Damage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for higher integration density, challenges arise in maintaining device reliability and performance due to unwanted etching and thickness non-uniformities of hard mask layers, which can lead to etching damage and rounding of top corners of layer stacks.
Innovation Solution
A method involving the formation of a semiconductor device with a first and second fin structure above a substrate, separated by a shallow trench isolation region, where a dielectric liner and hard mask layer are formed with non-uniform thicknesses, and an oxide capping layer is used to protect the hard mask layer during etching processes, reducing unwanted etching and maintaining uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but unwanted etching and thickness non-uniformities of hard mask layers occur leading to etching damage and rounding of top corners
Solution Approach 1:
A capping layer is deposited over the hard mask layer before etching processes to protect it from unwanted etching and thickness non-uniformities. This preliminary protective action prevents etching damage and maintains the uniformity of the hard mask layer during subsequent manufacturing steps.
Solution Approach 2:
The capping layer acts as an intermediary protective layer between the etching environment and the hard mask layer. This intermediate layer absorbs the harmful etching effects, preventing direct contact between the etchant and the hard mask layer, thereby maintaining its thickness uniformity and preventing corner rounding.
2Ease of manufacture
If etching processes are performed to pattern structures, then device components are formed, but unwanted etching of the hard mask layer occurs causing thickness non-uniformities and potential loss of shallow trench isolation region
Solution Approach 1:
The capping layer is deposited in advance before etching to provide protective coverage. This preliminary action ensures that the hard mask layer and underlying structures are protected during the necessary etching processes, maintaining device reliability while enabling effective patterning.
Solution Approach 2:
The capping layer serves as a mediator that allows etching processes to proceed for patterning while simultaneously protecting the hard mask layer from unwanted etching. This intermediate protection layer enables the etching process to achieve its patterning function without compromising device reliability.
3Manufacturing precision
If hard mask layer thickness is maintained for etching protection, then etching damage is reduced, but the layer complexity increases with additional deposition and etching steps
Solution Approach 1:
The protective structure is segmented into distinct functional layers: the hard mask layer for pattern definition and the capping layer for protection. This segmentation allows each layer to perform its specific function optimally, with the capping layer providing protection without interfering with the hard mask layer's patterning capability, thus managing complexity through functional separation.
Solution Approach 2:
The capping layer serves multiple functions: it protects the hard mask layer from unwanted etching, maintains thickness uniformity, and prevents loss of the shallow trench isolation region. By consolidating these protective functions into a single layer, the overall process complexity is managed while achieving comprehensive protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of etching damage to the hard mask layer, maintains its thickness uniformity, and enhances device reliability by preventing loss of the shallow trench isolation region, thereby preserving device characteristics and performance.
Implementation Method 1
unwanted etching and thickness non-uniformities of hard mask layers, which can lead to etching damage
Implementation Method 2
A method involving the formation of a semiconductor device with a first and second fin structure above a substrate, separated by a shallow trench isolation region, where a dielectric liner and hard mask layer are formed
Data Source
AI summary
A method includes forming a first fin structure and a second fin structure that protrude above a substrate, forming shallow trench isolation (STI) regions on opposing sides of each the first fin structure and the second fin structure, depositing a hard mask layer over the STI regions and top surfaces of the first fin structure and the second fin structure, and on sidewalls of the first fin structure and the second fin structure, depositing a capping layer over the hard mask layer, performing a first etching process to remove first portions of the capping layer and expose first portions of the hard mask layer, performing a second etching process to remove the exposed first portions of the hard mask layer, and forming a dummy gate structure over the first fin structure, the second fin structure, and remaining portions of the hard mask layer.