FinFET Fin Top Hard Mask for Dummy Gate Etch Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The fin top damage during fin sidewall etch back and dummy gate removing processes in FinFET fabrication poses a challenge in maintaining the integrity and complexity of integrated circuits, necessitating improved etching selectivity and protection methods.
Innovation Solution
The implementation of a fin top hard mask (FTHM) with high etching selectivity, potentially comprising high-K dielectric materials or amorphous silicon, to protect the fin top from damage during these processes, replacing or supplementing existing oxide and silicon nitride masks, and adjusting stress in material layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional oxide and silicon nitride masks are used during fin sidewall etch back and dummy gate removing processes, then the fabrication process can proceed with standard materials, but the fin top suffers from damage and loss during these processes
Solution Approach 1:
The patent introduces an amorphous silicon layer as an intermediary protective mask between the etching process and the fin top. This amorphous silicon layer serves as a mediator that absorbs the harmful effects of the etching process, preventing direct damage to the fin top while allowing the etching to proceed on the sidewalls. The amorphous silicon has appropriate etching selectivity, being more resistant to the etchant than the fin top material, thus protecting the fin top during fin sidewall etch back and dummy gate removing processes.
2Object-affected harmful factors
If a protective mask is applied to prevent fin top damage, then etching resistance is improved, but the device structure becomes more complex
Solution Approach 1:
The patent changes the material parameter of the protective mask from conventional oxide or silicon nitride to amorphous silicon. This parameter change provides superior etching resistance due to the different etching selectivity of amorphous silicon compared to the fin top material. The amorphous silicon can be deposited using standard PECVD processes, maintaining manufacturing simplicity while significantly improving protection during etching processes.
Solution Approach 2:
The amorphous silicon protective layer is applied in advance before the fin sidewall etch back and dummy gate removing processes. This preliminary action ensures that the fin top is protected from damage before the harmful etching processes occur. The layer is deposited conformally on the fin structure, and subsequent processing steps are designed to remove the protective layer after it has served its protective function, thus adding minimal complexity to the overall process.
3Manufacturing precision
If fin top protection is enhanced during etching processes, then manufacturing precision is improved, but the fabrication time increases
Solution Approach 1:
The amorphous silicon protective layer is designed to be self-removing or easily removable after serving its protective function. The layer can be removed using selective etching processes that target the amorphous silicon without affecting the fin top or other critical structures. This self-service characteristic allows the protective layer to perform its function automatically during the etching process and then be removed without requiring additional complex processing steps, thus minimizing the time penalty.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.