FinFET Hard Mask Patterning for Nodule Defect Reduction
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Solution Overview
Problem
The increasing trend of miniaturization in semiconductor devices leads to short channel effects, resulting in unexpected defects and reduced yields when forming finFET structures, which decreases productivity.
Innovation Solution
A method of fabricating semiconductor devices involves forming isolation regions with fin active regions, a sacrificial gate layer, and hard mask lines, followed by etching and selective epitaxial growth to create semiconductor layers that protrude from the fin active regions, while using a gate cut mask with specific opening configurations to reduce defects and improve productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to increase integration density, then device integration increases, but short channel effects increase causing defects and yield reduction
Solution Approach 1:
The patent introduces a third dimension by forming vertical fin structures instead of planar transistors. The fin active regions extend vertically from the substrate surface, creating a three-dimensional device architecture that improves channel control and reduces short channel effects while maintaining high integration density.
Solution Approach 2:
The patent segments the substrate into multiple isolated fin active regions using isolation regions. This segmentation allows independent formation and control of individual fin structures, enabling precise patterning and reducing defects caused by short channel effects in scaled devices.
2Reliability
If finFET structure is formed to reduce short channel effect, then channel control improves, but unexpected defects occur and productivity decreases
Solution Approach 1:
The patent performs preliminary actions by pre-forming isolation regions that define fin active region locations before fin formation, and by using sacrificial gate layers with hard mask lines positioned in advance. These preliminary structures guide subsequent processing steps, ensuring precise fin formation and gate alignment while reducing defects.
Solution Approach 2:
The patent introduces intermediary structures including sacrificial gate layers, hard mask lines, and gate cut masks that facilitate precise fin formation and gate patterning. These intermediary elements enable controlled material deposition and etching processes, reducing unexpected defects during finFET fabrication.
3Manufacturing precision
If hard mask lines are formed across all fin active regions, then patterning coverage is complete, but nodule defects occur at gate edges
Solution Approach 1:
The patent applies local quality by forming gate cut masks with different opening configurations for different regions. Edge gate cut openings have different dimensions than intermediate gate cut openings, allowing localized control of hard mask line exposure. This prevents nodule defects at gate edges while maintaining complete patterning coverage across all fin active regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces nodule defects and enhances productivity by optimizing the formation of semiconductor layers and gate structures, thereby improving the yield of semiconductor devices.
Implementation Method 1
The gate cut mask may be used as an etch mask to etch the hard mask lines
Implementation Method 2
selective epitaxial growth to form semiconductor layers that protrude from the fin active regions
Data Source
AI summary
Methods of fabricating semiconductor devices may include forming an isolation region that defines a plurality of fin active regions on a semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate, forming a first hard mask line that crosses first and second fin active regions and an edge bard mask line that crosses an edge fin active region, and forming a gate cut mask having a plurality of gate cut openings. The plurality of gate cut openings may include first and second gate cut openings that have a first width and are adjacent to the first and second fin active regions, respectively, and an edge gate cut opening that is adjacent to the edge fin active region and has a second width that is greater than the first width but smaller than twice a size of the first width.