FinFET Fin Top Hardmask for Lower Gate Capacitance

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Solution Overview

Problem

Existing FinFET devices face challenges in reducing gate height without affecting the operation of vertical channels, which leads to increased parasitic capacitance and potential etch damage during gate replacement processes.

Innovation Solution

The implementation of a fin top hardmask layer on top of the semiconductor fin allows for a reduction in gate height while maintaining proper channel operations. This hardmask also serves as an etch stop layer during gate replacement, preventing damage to the fin surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If gate height is reduced to decrease parasitic capacitance, then AC performance is improved, but vertical channel operation may be affected

Engineering Contradiction:

Improveparasitic capacitanceVSAvoidchannel operation

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent segments the gate structure into multiple components: a first gate electrode, a second gate electrode, and an intermediate layer between them. This segmentation allows the gate to be divided into functional zones where the first gate electrode controls the vertical channel while the second gate electrode manages parasitic capacitance effects, enabling independent optimization of both channel operation and AC performance

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical dimension to the gate structure by stacking gate electrodes at different heights above the fin. The first gate electrode is positioned closer to the fin while the second gate electrode is positioned higher, creating a three-dimensional gate configuration that provides additional control dimensions for managing both channel operation and parasitic capacitance without compromising either

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If gate replacement process is performed, then device fabrication is completed, but etch damage may occur to fin surface

Engineering Contradiction:

Improvegate replacementVSAvoidetch damage

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an etch stop layer as an intermediary component between the fin and the gate structure. This etch stop layer is specifically designed to be resistant to etch processes used during gate replacement, acting as a protective mediator that allows etching to proceed through overlying layers while stopping before reaching the fin surface, thus enabling gate replacement without fin damage

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The etch stop layer is formed in advance during the device fabrication process, before the gate replacement process is undertaken. This preemptive formation of the protective layer provides beforehand cushioning against potential etch damage, ensuring that when subsequent etching operations are performed during gate replacement, the fin surface is already protected by this resilient barrier layer

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12211921B2Method for forming FinFET devices with a fin top hardmask

Publication Date: 2025.01.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.