FinFET Height Control via Etching Stop Layer
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Solution Overview
Problem
Conventional FinFETs face challenges in controlling the height of semiconductor fins, leading to variations in channel width and adverse effects on device properties due to uncontrolled fin formation during manufacturing.
Innovation Solution
Incorporating an etching stop layer and an interlayer insulating layer to control the height of the semiconductor fin and prevent leakage, with a gate conductor covering at least two side surfaces of the fin, ensuring well-controlled channel width and mechanical support during the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the fin is formed by etching bulk silicon, then the FinFET structure can be created, but the height of the fin cannot be well controlled
Solution Approach 1:
The patent applies preliminary action by forming the etching stop layer before creating the fin structure. This stop layer is deposited in advance on the semiconductor substrate, establishing a predefined height reference that controls the final fin height during subsequent etching processes, thereby resolving the manufacturing precision issue.
Solution Approach 2:
The etching stop layer serves as an intermediary element between the semiconductor substrate and the fin structure. This intermediate layer mediates the fin formation process by providing a controlled etching boundary, allowing precise fin height control without complicating the overall manufacturing process.
2Reliability
If the gate extends over the top surface and two side surfaces of the fin (triple-gate), then better short channel effect suppression is achieved, but the channel width becomes more sensitive to fin height variations
Solution Approach 1:
By establishing the etching stop layer in advance, the fin height is predetermined before gate formation. This preliminary height control ensures that when the gate is formed to extend over the fin surfaces, the channel width remains consistent and predictable, reducing sensitivity to height variations while maintaining effective short channel effect suppression.
3Ease of manufacture
If the fin height is not well controlled, then manufacturing is simpler, but the channel width varies adversely affecting device properties
Solution Approach 1:
The etching stop layer acts as an intermediary that decouples the simplicity of the etching process from the precision of the fin height control. The layer enables straightforward etching operations while simultaneously ensuring consistent fin height and channel width, thus maintaining manufacturing simplicity without sacrificing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for precise control of the fin height and channel width, enhancing the reliability and yield of FinFETs by preventing leakage and providing mechanical support, thus addressing the short channel effects and manufacturing variability.
Implementation Method 1
an etching stop layer on a semiconductor substrate; because etching stops at the top of the etching stop layer when the semiconductor fin is formed from the semiconductor layer
Implementation Method 2
an interlayer insulating layer adjoining the etching stop layer below the gate dielectric layer, and separating the gate conductor from the etching stop layer and the semiconductor fin
Implementation Method 3
a gate dielectric layer between the gate conductor and the semiconductor fin
Implementation Method 4
forming a source region and a drain region by implanting ions at two ends of the semiconductor fin
Data Source
AI summary
A FinFET and a method for manufacturing the same are disclosed. The FinFET comprises an etching stop layer on a semiconductor substrate; a semiconductor fin on the etching stop layer; a gate conductor extending in a direction perpendicular to a length direction of the semiconductor fin and covering at least two side surfaces of the semiconductor fin; a gate dielectric layer between the gate conductor and the semiconductor fin; a source region and a drain region which are provided at two ends of the semiconductor fin respectively; and an interlayer insulating layer adjoining the etching stop layer below the gate dielectric layer, and separating the gate conductor from the etching stop layer and the semiconductor fin. A height of the fin of the FinFET is approximately equal to a thickness of a semiconductor layer for forming the semiconductor fin.