FinFET Gate Density via High Mobility Material Integration

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Solution Overview

Problem

Integrated circuits with fin field effect transistors (finFETs) achieve high gate density but lack the transistor performance offered by planar transistors using high mobility materials like III-V materials or germanium, making it difficult to integrate these materials into high-density integrated circuits.

Innovation Solution

The formation of n-channel and p-channel finFETs by creating separate fin epitaxial layers and using a fin etch process to define and recess the fin structures, followed by the deposition of gate dielectric layers and gates, allowing for the integration of high mobility materials like germanium to enhance on-state current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If fin field effect transistors (finFETs) are used to achieve high gate density, then gate density is improved, but transistor performance using high mobility materials cannot be integrated

Engineering Contradiction:
Improvegate densityVSAvoidintegration of high mobility materials
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent applies local quality by forming different polarity fin epitaxial layers (n-channel and p-channel) in separate areas with distinct material compositions. The n-channel fin epitaxial layer contains higher germanium content (e.g., 80-90% Ge) while the p-channel fin epitaxial layer has lower germanium content (e.g., 50-70% Ge), allowing each region to be optimized for its specific transistor type while maintaining high gate density in the overall integrated circuit

Inventive Principle:
Principle #3Local quality

2Reliability

If planar transistors with high mobility materials are used, then transistor performance is improved, but gate density is reduced

Engineering Contradiction:
Improvetransistor performanceVSAvoidgate density
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent transitions from planar transistor geometry to three-dimensional finFET structures. By forming vertical fins that extend upward from the substrate, the gate wraps around the fin structure, effectively increasing the gate length and controlling capability without increasing the planar footprint. This dimensional change enables both high gate density and improved transistor performance with high mobility materials

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the integration of high mobility materials into finFETs, providing improved on-state current for both n-channel and p-channel finFETs, which surpasses the performance of silicon finFETs, thus achieving higher speed and density in integrated circuits.

Implementation Method 1

A fin etch process removes epitaxial material in areas exposed by the fin mask to leave the n-channel fin and the p-channel fin

Methodology Applied
Scientific EffectSelective etching:

Implementation Method 2

A planarizing process planarizes the isolation oxide layer proximate to top surfaces of the n-channel fin and the p-channel fin

Methodology Applied
Scientific EffectPlanarization:

Implementation Method 3

The isolation oxide layer is recessed by a subsequent etchback process, exposing the n-channel fin and the p-channel fin

Methodology Applied
Scientific EffectSelective etching:

Implementation Method 4

Gate dielectric layers and gates are formed over the exposed n-channel fin and the p-channel fin

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS20210225711A1High mobility transistors
Publication Date: 2021.07.22 TEXAS INSTRUMENTS INC
  • US20210225711A1 patent drawing
  • US20210225711A1 patent drawing
  • US20210225711A1 patent drawing

AI summary

An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.