FinFET Gate Dielectric Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating three-dimensional designs, such as FinFETs, due to issues related to short channel effects and the complexity of gate dielectric layer formation, which affects device performance and density.
Innovation Solution
The proposed solution involves a multi-layer gate dielectric structure comprising a high-k dielectric material and a different dielectric material, along with a metal gate stack, to reduce the aspect ratio and parasitic capacitance, and includes a method for forming sacrificial gate structures and sidewall spacers to define gate cavities and electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer gate dielectric structure is used, then the fabrication process is simpler, but the device performance and density are reduced due to short channel effects
Solution Approach 1:
The gate dielectric layer is divided into multiple segments: a first gate dielectric layer (e.g., high-k material like HfO2) and a second gate dielectric layer (e.g., low-k material like SiO2). This segmentation allows each layer to perform different functions - the first layer provides high capacitance for gate control while the second layer reduces parasitic capacitance and improves planarization, thereby resolving the contradiction between structural simplicity and device performance.
2Productivity
If the aspect ratio of FinFET is reduced, then device density improves, but parasitic capacitance increases
Solution Approach 1:
The gate dielectric structure uses composite materials combining high-k and low-k dielectric layers. The high-k material (first layer) enables reduced aspect ratio FinFETs by providing sufficient gate control with thinner effective oxide equivalent thickness, while the low-k material (second layer) reduces parasitic capacitance between gate and source/drain regions, thus resolving the contradiction between device density and parasitic capacitance.
3Reliability
If complex gate dielectric layer formation is used, then device performance improves, but fabrication complexity increases
Solution Approach 1:
The first gate dielectric layer (high-k material) is formed preliminarily before the second gate dielectric layer (low-k material). This preliminary action allows the high-k layer to establish the primary gate control function, while the subsequently formed low-k layer adds parasitic capacitance reduction and planarization benefits. The sacrificial gate structure is also formed preliminarily to define the gate cavity, simplifying the overall fabrication sequence.
4Reliability
If high-k dielectric material is used, then gate control improves, but planarization difficulty increases
Solution Approach 1:
The low-k dielectric layer (second layer) is nested over the high-k dielectric layer (first layer) in a conformal manner. This nested structure allows the smoother low-k material to cover the surface irregularities of the high-k layer, providing automatic planarization. The sacrificial gate structure is also nested within the gate cavity, enabling precise definition of the gate electrode region while simplifying the overall fabrication process.
Data Source
AI summary
A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.