FinFET HV Region Structure for Precise Fin Etching Control
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Solution Overview
Problem
The miniaturization of semiconductor devices poses challenges in the fabrication of fin field effect transistors (FinFETs), particularly in precisely defining the fin structure and controlling etching processes, leading to issues like fin collapse or over-etching.
Innovation Solution
A semiconductor device is designed with a substrate having logic and high-voltage regions, featuring fin-shaped structures formed using sidewall image transfer and selective epitaxial growth, with gate structures and epitaxial layers optimized for both regions to improve control and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the fin structure width and pitch are shrunk to achieve continuous miniaturization, then the device size is reduced, but the fabrication precision deteriorates leading to fin collapse or over-etching
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before the fin structure, which serves as a template to guide subsequent self-aligned etching processes. This pre-formed mandrel enables precise fin definition without requiring direct lithographic patterning at the final fin dimensions, thereby achieving miniaturization while maintaining fabrication precision through self-aligned processes that eliminate alignment errors
Solution Approach 2:
The patent introduces a mandrel as an intermediary structure that mediates between the lithography step and the final fin structure. This intermediate mandrel allows the use of less precise lithography for defining the mandrel position, while the subsequent self-aligned etching processes transfer this pattern to the fin structure with high precision, effectively decoupling the lithography precision requirement from the final fin dimension control
2Reliability
If the etching time is extended to ensure complete fin formation, then the fin structure is fully formed, but over-etching occurs damaging the substrate
Solution Approach 1:
The patent implements feedback control through selective etching processes that use the mandrel structure and sacrificial layers as etch stop references. The etching process is designed to stop automatically when it reaches predefined interfaces (such as the mandrel-substrate interface or sacrificial layer boundaries), providing real-time process control that prevents over-etching while ensuring complete fin formation. This self-limiting etch approach eliminates the need for extended etching times
Solution Approach 2:
The patent prepares sacrificial layers and mandrel structures in advance that serve as built-in etch stop references. These pre-formed structures create physical boundaries that automatically limit the etching depth, ensuring that the etching process stops exactly when the fin structure is complete without penetrating into the substrate. This preliminary preparation of etch boundaries prevents over-etching damage while guaranteeing complete fin formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the precision and efficiency of FinFET fabrication, addressing issues like fin collapse and over-etching, and improves the performance of semiconductor devices by optimizing the structure and process for both logic and high-voltage regions.
Implementation Method 1
selective epitaxial growth
Data Source
AI summary
A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first fin-shaped structure between the first epitaxial layer and the substrate, and a first contact plug between the first epitaxial layer and the second epitaxial layer. Preferably, the first gate structure includes a gate dielectric layer, top surfaces of the gate dielectric layer and the first fin-shaped structure are coplanar, and a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug.


