FinFET and HV Region Layout for Precise Fin Patterning
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Solution Overview
Problem
The miniaturization of semiconductor devices poses challenges in the fabrication of fin field effect transistors (FinFETs), particularly in precisely defining the fin structure and controlling etching processes, leading to issues like fin collapse and over-etching, which affect efficiency.
Innovation Solution
A semiconductor device design that includes a substrate with defined logic and high-voltage regions, where fin-shaped structures are formed using sidewall image transfer and selective epitaxial growth processes, resulting in stripe-shaped structures on the logic region and ring-shaped structures on the high-voltage region, with epitaxial layers and contact plugs strategically positioned to improve control and reduce fabrication limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the width of each fin and the pitch between fins are shrunk to enable continuous miniaturization, then the device density and integration level are improved, but the fabrication process becomes more difficult and leads to fin collapse or over-etching issues
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before the fin etching process. The mandrel serves as a pre-formed template that defines the fin pattern, allowing subsequent self-aligned spacer formation and etching. This preliminary structure enables precise fin definition at scaled dimensions without requiring direct lithographic patterning at the final fin pitch, thereby resolving the manufacturing precision issue while maintaining high device density
Solution Approach 2:
The patent introduces a mandrel as an intermediary structure that mediates between the lithographic pattern and the final fin structure. The mandrel acts as a temporary template that is later removed, having served its purpose of defining the fin pattern through self-aligned spacer formation. This intermediary approach enables precise fin definition at scaled dimensions while avoiding direct lithographic limitations
2Ease of manufacture
If current mask and lithography techniques are used to define fin structure position, then the fabrication process is simpler, but the position definition precision and etching control are insufficient
Solution Approach 1:
The mandrel structure is formed in advance as a preliminary template that defines the fin pattern. This preliminary action allows the fin position to be defined with high precision through self-aligned spacer formation, eliminating the need for direct lithographic patterning at the final fin pitch. The mandrel serves as a precise positioning reference that is later removed, having accomplished its pattern definition function
Solution Approach 2:
The patent transitions from two-dimensional lithographic patterning to a three-dimensional self-aligned spacer formation process. The mandrel provides a vertical reference structure that enables precise lateral fin positioning through spacer thickness control. This dimensional transition allows high-precision fin definition by leveraging vertical spacer formation rather than relying solely on lateral lithographic resolution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision and efficiency of FinFET fabrication, addressing issues like negative bias temperature instability (NBTI) and enabling the integration of FinFET and high-voltage devices by maintaining precise control over fin structure formation and epitaxial growth, thereby improving device performance in nano-scaled semiconductor technology.
Implementation Method 1
selective epitaxial growth processes
Data Source
AI summary
A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.