FinFET Hybrid Substrate Crystal Orientation
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Solution Overview
Problem
As FinFET devices scale down, there is a risk of fin width scaling leading to short channel effects, resulting in mobility degradation, necessitating an increase in carrier mobility in semiconductor materials to maintain performance.
Innovation Solution
The fabrication process involves forming fins on semiconductor substrates with different crystal orientations, using a combination of silicon and SiGe materials, and epitaxial growth to enhance carrier mobility, along with a gate structure that crosses over the fins to form channel regions and source/drain regions, and the use of high-k dielectric layers and work function metal layers in replacement metal gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fin width is scaled down to increase device density, then device density is improved, but carrier mobility deteriorates due to short channel effects
Solution Approach 1:
The patent changes the crystal orientation parameter of the fin structure from conventional <100> to <110> orientation. This parameter change in the crystal structure fundamentally alters the carrier transport properties, enabling high mobility even at scaled-down fin dimensions, thus resolving the contradiction between device density and carrier mobility
Solution Approach 2:
The patent employs a composite structure combining silicon-on-insulator substrate with epitaxially grown silicon fins having specific crystal orientation. This composite approach leverages the advantages of both the substrate and the oriented fin structure to maintain carrier mobility while enabling scaling
2Productivity
If fin width is scaled down to increase device density, then device density is improved, but device performance deteriorates
Solution Approach 1:
By changing the crystal orientation parameter to <110>, the patent fundamentally alters the device physics to maintain performance at scaled dimensions, resolving the contradiction between density and performance
3Ease of manufacture
If conventional silicon substrate is used, then manufacturing simplicity is maintained, but carrier mobility is insufficient for scaled devices
Solution Approach 1:
The patent changes the crystal orientation parameter from conventional <100> to <110> while maintaining compatibility with existing silicon manufacturing processes, thus improving mobility without sacrificing ease of manufacture
Solution Approach 2:
The patent performs preliminary epitaxial growth to establish the correct <110> crystal orientation before fin formation, ensuring the desired properties are built into the structure from the outset rather than requiring complex post-processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility and device performance by optimizing the crystal orientation and material composition of the fins, reducing short channel effects and enhancing the performance of FinFET devices.
Implementation Method 1
bonding a second semiconductor substrate onto a first semiconductor substrate
Implementation Method 2
epitaxial growth to enhance carrier mobility
Data Source
AI summary
A FinFET semiconductor structure includes first fins and second fins extended from a semiconductor substrate, and a gate structure disposed over the first fins and the second fins. Each first fin includes a first semiconductor portion connected to the semiconductor substrate and a second semiconductor portion over the semiconductor substrate. Each second fin includes the first semiconductor portion connected to the semiconductor substrate, the second semiconductor portion, and at least one spacer at least partially disposed between the first semiconductor portion and the second semiconductor portion. The semiconductor substrate and the first semiconductor portion respectively have a surface oriented on a first crystal plane, the second semiconductor portion has a surface oriented on a second crystal plane, wherein the first crystal plane is oriented differently than the second crystal plane.