FinFET Impurity Region Segmentation for Short Channel Effect Control
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Solution Overview
Problem
The increased integration of semiconductor devices leads to a short channel effect in field effect transistors, which necessitates the development of fin FETs with three-dimensional channel structures to overcome this disadvantage.
Innovation Solution
A semiconductor device is designed with active fins protruding from a substrate, featuring gate electrodes and impurity regions formed in both epitaxial and non-epitaxial layers, where the second impurity region has a greater width and is not entirely formed in an epitaxial layer, with specific configurations to enhance performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration level is increased, then device density is improved, but short channel effect occurs in FETs
Solution Approach 1:
The patent transitions from a planar FET structure to a FinFET structure with a three-dimensional fin channel. The fin protrudes vertically from the substrate, creating a height dimension that enables better gate control over the channel while maintaining high integration density. This dimensional change allows the gate to control carriers from multiple surfaces of the fin, effectively suppressing short channel effects even at advanced technology nodes.
2Reliability
If fin FET structure is used, then short channel effect is overcome, but manufacturing complexity increases
Solution Approach 1:
The patent divides the impurity regions into multiple segments with different characteristics. The first impurity region is formed entirely within the epitaxial layer, while the second impurity region extends into the substrate. This segmentation allows each region to be optimized independently for its specific function, simplifying the overall device design while maintaining effective short channel control.
Solution Approach 2:
The patent applies different impurity concentrations and distributions to different regions of the FinFET structure. The first impurity region has a specific concentration profile within the epitaxial layer, while the second impurity region has a different profile extending into the substrate. This local quality variation optimizes carrier control in each region without requiring complex global modifications to the entire device structure.
3Reliability
If asymmetric impurity regions are used, then operating characteristics are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the first impurity region entirely within the epitaxial layer before final device completion. This preliminary action establishes a controlled impurity distribution that serves as a foundation for subsequent processing steps. By pre-forming this region with precise boundaries defined by the epitaxial layer thickness, the patent reduces the precision requirements for later impurity formation steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed semiconductor device structure improves operating characteristics and reliability by effectively managing the short channel effect, enabling high-speed operation with low voltage and increased integration levels.
Implementation Method 1
a first epitaxial layer portion on the active fin
Data Source
AI summary
In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.