FinFET Source/Drain Insulator Layer for Leakage and Capacitance
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Solution Overview
Problem
As semiconductor devices, such as FinFETs, continue to shrink in feature size, they face challenges with increased leakage current and capacitance, which affect performance and integration density, necessitating innovative solutions to improve device reliability and speed.
Innovation Solution
The incorporation of an insulator layer at the bottom of the source/drain regions in FinFETs reduces leakage current and capacitance by allowing an air gap to form between the insulator layer and the epitaxial material, enabling higher device performance and speed without the need for a conventional lower doped layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain regions are used without an insulator layer, then the manufacturing process is simpler, but leakage current increases and device reliability deteriorates
Solution Approach 1:
The source/drain region is segmented into multiple functional layers: an insulator layer at the bottom, epitaxial material layers above it, and gaps between them. This segmentation allows the insulator layer to specifically address leakage current at the interface with the substrate while the epitaxial layers provide conductive pathways, thus improving reliability without requiring complete redesign of the entire source/drain structure.
Solution Approach 2:
The insulator layer acts as an intermediary between the substrate and the epitaxial material, preventing direct contact that would cause leakage current. This intermediary layer blocks unwanted electrical leakage while allowing the epitaxial material to maintain its conductive function, thereby improving device reliability without significantly complicating the overall structure.
2Productivity
If feature size is reduced to improve integration density, then more components can be integrated, but leakage current and capacitance increase
Solution Approach 1:
The insulator layer is selectively placed at the bottom of the source/drain regions where leakage current is most problematic, particularly at the interface with the substrate. This local application of insulation provides targeted leakage reduction without requiring insulator layers throughout the entire device structure, thus managing energy loss while maintaining integration density.
Solution Approach 2:
The solution addresses leakage current by adding a vertical dimension to the source/drain structure through the insulator layer and gaps, rather than trying to control leakage through lateral dimensions alone. This vertical insulation approach effectively reduces leakage current and capacitance even as horizontal feature sizes are reduced to improve integration density.
3Reliability
If an insulator layer with gaps is added to reduce leakage current, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The insulator layer is formed first, before the epitaxial material is deposited. This preliminary action establishes the insulation framework in advance, allowing subsequent epitaxial growth to occur in defined regions. By preparing the insulator structure beforehand, the manufacturing process manages complexity through staged fabrication rather than attempting to create the complete structure in a single step.
Solution Approach 2:
The gaps between the insulator layer and epitaxial material are formed through self-aligned processes where the epitaxial material grows around the insulator structures. This self-service approach allows the manufacturing process to automatically create the necessary gaps and alignments without requiring additional complex patterning steps, thus improving device performance while limiting the increase in manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and reliability of FinFET devices by reducing leakage current and capacitance, leading to improved speed and efficiency, while also simplifying the manufacturing process by omitting the conventional lower doped layer.
Implementation Method 1
the insulator layer at the bottom of the source/drain regions can cause an air gap to form between the insulator layer and the epitaxial material of the source/drain regions
Data Source
AI summary
An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source/drain region in the first fin and adjacent the first gate spacer. The first source/drain region including a first insulator layer on the first fin, and a first epitaxial layer on the first insulator layer.