FinFET Interconnect Adhesion Layer Prevents Delamination

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing interconnect structures in semiconductor devices face challenges in achieving satisfactory performance due to issues such as poor adhesion between conductive features and dielectric layers, leading to delamination and reduced device performance.

Innovation Solution

A dual damascene process is employed to form a trench-via structure with an adhesion layer between the conductive feature and the dielectric layer, which is a discontinuous layer extending on the sidewalls and bottom surfaces of the openings, enhancing adhesion and preventing delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dual damascene process with adhesion layer is used, then adhesion between conductive feature and dielectric layer is improved, but device complexity increases

Engineering Contradiction:
Improveadhesion between conductive feature and dielectric layerVSAvoidcomplexity of interconnect structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

An adhesion layer is introduced as an intermediary between the conductive feature and the dielectric layer. This adhesion layer serves as a mediator that enhances the bonding interface and prevents delamination, directly resolving the adhesion problem while maintaining structural integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The interconnect structure employs composite materials by combining multiple layers including the adhesion layer, conductive feature, and dielectric layer. This composite approach allows each layer to contribute its specific properties, with the adhesion layer providing enhanced bonding capabilities that neither the conductive feature nor dielectric layer could achieve alone.

Inventive Principle:
Principle #40Composite materials

2Reliability

If adhesion layer is added to prevent delamination, then reliability is improved, but manufacturing process complexity increases

Engineering Contradiction:
Improveprevention of delaminationVSAvoidease of manufacturing interconnect structure
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The adhesion layer is applied in advance, before the conductive feature is formed, as part of the dual damascene process. This preliminary action ensures that the adhesion interface is established before subsequent processing steps, preventing delamination issues that would be difficult to address later in manufacturing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The adhesion layer acts as an intermediary that simplifies the overall manufacturing by providing a reliable bonding interface that prevents delamination, reducing the need for additional corrective processes or quality control measures to address adhesion failures.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The adhesion layer improves the connection between the conductive feature and the dielectric layer, enhancing the semiconductor device's performance by preventing delamination and ensuring reliable electrical connectivity.

Implementation Method 1

A dual damascene process is employed to form a trench-via structure with an adhesion layer between the conductive feature and the dielectric layer, which is a discontinuous layer extending on the sidewalls and bottom surfaces of the openings, enhancing adhesion and preventing delamination.

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS10134669B2Method for forming fin field effect transistor (FinFET) device structure with interconnect structure
Publication Date: 2018.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10134669B2 patent drawing
  • US10134669B2 patent drawing
  • US10134669B2 patent drawing

AI summary

A semiconductor device structure includes a first metal layer formed over a substrate and an interconnect structure formed over the first metal layer. The interconnect structure includes an upper portion, a middle portion and a lower portion, the middle portion is connected between the upper portion and the lower portion. The upper portion and the lower portion each have a constant width, and the middle portion has a tapered width which is gradually tapered from the upper portion to the lower portion.