FinFET Interconnect Barrier Structures for Selective Etching
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Solution Overview
Problem
In integrated circuit fabrication, particularly for fin-type field-effect transistors (FinFETs), existing etching techniques like plasma reactive-ion etching (RIE) cause damage to materials, leading to electrical shorts and non-uniformity in interconnect structures due to insufficient selectivity and confinement of epitaxial growth within trenches.
Innovation Solution
The method involves forming first and second barrier structures along opposing sides of fins, using different materials than the insulating material, to facilitate isotropic etching that selectively removes the insulating material without affecting the barrier structures, thereby confining the interconnect structure to a defined dimension and preventing unwanted epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If plasma reactive-ion etching is used to remove insulating material, then etching capability is improved, but material damage occurs leading to electrical shorts and non-uniformity
Solution Approach 1:
The patent changes the etching method from plasma reactive-ion etching to isotropic etching, altering the etching parameters and mechanism to achieve selective removal of insulating material without damaging the barrier structures or causing electrical shorts
Solution Approach 2:
The patent introduces barrier structures made of materials different from the insulating material as intermediary elements that protect underlying structures during etching, preventing direct contact between the etchant and sensitive materials
2Speed
If plasma reactive-ion etching is used, then etching speed is improved, but selectivity is reduced causing non-uniform interconnect structures
Solution Approach 1:
The patent transitions from anisotropic plasma reactive-ion etching to isotropic etching, changing the etching parameters to achieve uniform material removal while maintaining adequate etching speed through process optimization
Solution Approach 2:
The barrier structures serve as protective intermediaries that ensure uniform etching by preventing over-etching and protecting adjacent structures, thereby achieving uniform interconnect structures
3Ease of manufacture
If epitaxial growth is performed without confinement, then interconnect structure formation is simplified, but unwanted epitaxial growth occurs outside defined dimensions
Solution Approach 1:
The barrier structures act as physical intermediaries that confine epitaxial growth to defined dimensions, preventing unwanted growth while maintaining ease of manufacture through the natural epitaxial process
Solution Approach 2:
The patent segments the growth space using barrier structures, creating defined regions where epitaxial growth is permitted and regions where it is prevented, achieving precise spatial control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more precise and damage-free formation of interconnect structures, ensuring uniformity and preventing electrical shorts by confining epitaxial growth within defined dimensions, thus adapting to smaller feature sizes without compromising design rules.
Implementation Method 1
the first and second barrier structures confine the interconnect structure to a defined dimension transverse to the at least one fin
Implementation Method 2
using different materials than the insulating material, to facilitate isotropic etching that selectively removes the insulating material without affecting the barrier structures
Data Source
AI summary
Methods and interconnect structures for circuit structure transistors are provided. The methods include, for instance: providing one or more fins above a substrate, and an insulating material over the fin(s) and the substrate; providing barrier structures extending into the insulating material, the barrier structures being disposed along opposing sides of the fin(s); exposing a portion of the fin(s) and the barrier structures; and forming an interconnect structure extending over the fin(s), the barrier structures confining the interconnect structure to a defined dimension transverse to the fin(s). Exposing the portion of the fin(s) and barrier structures may include isotropically etching the insulating material with an etchant that selectively etches the insulating material without affecting a barrier material of the barrier structures.