FinFET Isolated Oxide Layer Mitigates Dopant Diffusion

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Solution Overview

Problem

Current bulk FinFETs utilize a punch through stopper layer that leads to undesired channel doping and performance degradation due to variation in threshold voltage and mobility, caused by dopant diffusion and parasitic channel formation.

Innovation Solution

A FinFET device architecture with an isolated oxide layer separating the bottom and active top fin portions, formed by reacting silicon and germanium in a sacrificial layer with germanium oxide to create a concentrated germanium region, which is then oxidized to form a mixed oxide region, reducing dopant diffusion and parasitic channel formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a punch through stopper layer is used in bulk FinFETs, then channel doping is achieved, but performance degradation occurs due to dopant diffusion and parasitic channel formation

Engineering Contradiction:
Improvechannel dopingVSAvoiddevice performance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent removes the punch through stopper layer entirely and replaces it with an isolated oxide layer formed by oxidizing a sacrificial layer. This extraction eliminates the source of dopant diffusion and parasitic channel formation while maintaining the necessary electrical isolation and threshold voltage control in scaled FinFET devices.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the material parameter from a doped semiconductor stopper layer to an oxide layer. By oxidizing the sacrificial layer (which contains silicon and germanium), the material transforms from a conductive/semiconductive state to an insulating oxide state, fundamentally changing the electrical characteristics and eliminating dopant diffusion issues.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If device dimensions are scaled down to increase density, then capacity increases, but threshold voltage variation and mobility degradation worsen

Engineering Contradiction:
Improvedevice densityVSAvoidthreshold voltage control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The isolated oxide layer acts as an intermediary structure between the source/drain regions and the channel. It provides a controlled interface that prevents unwanted dopant diffusion into the channel while maintaining proper electrical isolation, thereby stabilizing threshold voltage in scaled devices without compromising density.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If a sacrificial layer is oxidized to form an isolated oxide layer, then dopant diffusion is reduced, but process complexity increases

Engineering Contradiction:
Improvedopant diffusion controlVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The sacrificial layer is deposited and patterned in advance, before the main FinFET fabrication steps. This preliminary action establishes the isolated oxide layer framework early in the process, enabling subsequent dopant diffusion control without adding significant complexity to the main fabrication sequence. The sacrificial layer is later oxidized in a controlled manner to complete the isolation structure.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The isolated oxide layer reduces dopant diffusion and parasitic channel formation, thereby improving device performance by stabilizing the threshold voltage and mobility.

Implementation Method 1

oxidize the silicon in the sacrificial layer to form a concentrated germanium region

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

The structure is annealed in an inert environment to reduce the germanium oxide in the germanium oxide layer and oxidize the silicon in the sacrificial layer to form a concentrated germanium region

Methodology Applied
Scientific EffectReduction: Reduction

Implementation Method 3

The structure is then oxidized to convert the germanium in the concentrated germanium region to silicon germanium oxide thereby forming a mixed oxide region

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS10680083B2Oxide isolated fin-type field-effect transistors
Publication Date: 2020.06.09 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10680083B2 patent drawing
  • US10680083B2 patent drawing
  • US10680083B2 patent drawing

AI summary

According to an embodiment of the present invention, a semiconductor structure includes a semiconductor substrate and a plurality of fins located on the semiconductor substrate. The plurality of fins each independently includes a bottom fin portion, a top fin portion layer, and an isolated oxide layer located in between the bottom fin portion and the top fin portion layer in the y-direction parallel to the height of the plurality of fins. The isolated oxide layer includes a mixed oxide region located in between oxidized regions in an x-direction perpendicular to the height of the plurality of fins.