FinFET Isolation Structure With Bi-Layer Dielectric for Lower RC Delay
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Solution Overview
Problem
The increasing complexity of semiconductor manufacturing due to scaled-down dimensions leads to higher parasitic capacitances in semiconductor devices with finFETs, which adversely impact device performance by increasing RC time delay.
Innovation Solution
The implementation of isolation structures with a bi-layer dielectric stack of silicon nitride (SiN) and silicon oxide (SiO2) or SiO2-based materials, which reduces the dielectric constant of the isolation structure by 30% to 50% compared to structures with only SiN fill, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation structures with SiN fill are used in scaled-down finFET devices, then device isolation is achieved, but parasitic capacitance increases causing higher RC time delay
Solution Approach 1:
The patent applies composite materials by combining silicon nitride (SiN) and silicon oxide (SiO2) in a bi-layer structure. The SiN layer provides isolation functionality while the SiO2 layer reduces the overall dielectric constant of the isolation structure, thereby reducing parasitic capacitance while maintaining device isolation
Solution Approach 2:
The patent changes the dielectric parameter by introducing SiO2 material with lower dielectric constant into the isolation structure. This parameter change reduces the overall capacitance of the isolation structure, directly addressing the harmful parasitic capacitance effect while preserving the isolation function
2Productivity
If scaling down semiconductor device dimensions is pursued to increase storage capacity and processing speed, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the isolation structure into two distinct layers: a SiN layer for isolation functionality and a SiO2 layer for capacitance reduction. This segmentation allows each layer to perform its specific function optimally, enabling scaled-down devices to maintain performance while managing manufacturing complexity through modular structure design
3Reliability
If SiN fill is used in isolation structures, then device isolation is provided, but RC time delay increases due to high dielectric constant
Solution Approach 1:
The patent uses composite materials combining SiN and SiO2 layers. The SiN layer maintains isolation effectiveness while the SiO2 layer reduces the dielectric constant, thereby reducing RC time delay. The composite structure achieves both isolation effectiveness and reduced time delay simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance in semiconductor devices, improving device performance by minimizing RC time delay and reducing manufacturing costs associated with process variability.
Implementation Method 1
The implementation of isolation structures with a bi-layer dielectric stack of silicon nitride (SiN) and silicon oxide (SiO2) or SiO2-based materials, which reduces the dielectric constant of the isolation structure by 30% to 50% compared to structures with only SiN fill, thereby reducing parasitic capacitance
Data Source
AI summary
A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.