FinFET Isolation Structure for High Breakdown Voltage
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Solution Overview
Problem
FinFET devices face limitations in achieving high drain-to-source breakdown voltage, which restricts their performance and scalability in advanced semiconductor integrated circuits.
Innovation Solution
Incorporating a second isolation structure embedded in the fin structure's upper portion, surrounded by a first isolation structure, enhances the breakdown voltage by creating non-overlapping regions for drain and source contacts, allowing for a higher voltage range from 1.8 V to 10 V.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a conventional FinFET structure is used, then the device size is reduced and current capacity is increased, but the drain-to-source breakdown voltage is limited
Solution Approach 1:
The isolation structure is divided into two distinct parts: a first isolation structure surrounding the lower portion of the fin structure, and a second isolation structure embedded in the upper portion of the fin structure. This segmentation allows independent optimization of each isolation region, enabling the lower isolation to provide basic electrical isolation while the upper isolation creates non-overlapping contact regions that enhance breakdown voltage without increasing overall device footprint.
Solution Approach 2:
The patent transitions from a planar isolation approach to a three-dimensional isolation architecture. The second isolation structure is embedded within the upper portion of the fin structure, utilizing the vertical dimension to create non-overlapping drain and source contact regions. This vertical arrangement increases the effective isolation distance and breakdown voltage path without expanding the lateral device dimensions, thus maintaining scalability.
2Reliability
If isolation structures are added to increase breakdown voltage, then the drain-to-source breakdown voltage is improved, but the device complexity increases
Solution Approach 1:
The patent combines the isolation function with the fin structure geometry itself. The second isolation structure is embedded directly in the upper portion of the fin structure, merging the isolation element with the active device structure rather than adding it as a separate external component. This integration reduces the number of discrete elements and simplifies the overall device architecture while achieving enhanced breakdown voltage through the non-overlapping contact regions.
Data Source
AI summary
A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over the upper surface of the substrate, and a second isolation structure. The fin structure extends along a first direction and comprising a lower portion and an upper portion. The first isolation structure surrounds the lower portion of the fin structure. The second isolation structure is at least partially embedded in the upper portion of the fin structure.


