FinFET Sidewall Spacers for Isolation Bump Etch Control
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Solution Overview
Problem
As fin-type field effect transistor (FINFET) size decreases and density increases, it becomes challenging to form FINFETs without compromising robustness, particularly due to issues with source/drain contact formation, where the angle of epitaxial source/drain regions relative to the semiconductor fin can be significant, leading to unlanded contacts and defective devices.
Innovation Solution
A method involving the formation of trench isolation regions with silicon dioxide bumps and sidewall spacers is used to control the shape of isolation bumps, preventing lateral etching and ensuring that source/drain recesses have semiconductor surfaces on opposing sides and bottoms, thereby minimizing the angle of epitaxial source/drain regions and reducing the risk of unlanded contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FINFET size is decreased and density is increased, then device scalability and density are improved, but manufacturing precision and robustness deteriorate due to difficulty in forming FINFETs without compromising quality
Solution Approach 1:
The semiconductor fin is divided into multiple active device regions by trench isolation regions, allowing independent processing and optimization of each region. This segmentation enables precise control of source/drain recesses in each active region without affecting adjacent regions, thereby maintaining manufacturing precision while increasing overall device density.
Solution Approach 2:
Different regions of the semiconductor fin are given different properties: active device regions contain FINFETs with specific channel characteristics, while trench isolation regions provide electrical isolation. The source/drain recesses are selectively formed only in active regions, ensuring that each local area has the optimal quality for its specific function, thus maintaining precision while enabling high density.
2Productivity
If source/drain recesses are formed adjacent to trench isolation regions, then device integration is improved, but the angle of epitaxial source/drain regions becomes significant, leading to unlanded contacts
Solution Approach 1:
The method performs preliminary actions by first forming the trench isolation regions to define active device regions, then selectively forming source/drain recesses only in those defined active regions. This preliminary definition ensures that subsequent epitaxial growth occurs only where needed, with proper geometry, preventing unlanded contacts while maintaining high integration. The sidewall spacers are also formed preliminarily to protect adjacent areas during etching.
Solution Approach 2:
Sidewall spacers act as intermediary protective structures formed on the isolation bumps. These spacers prevent lateral etching during source/drain recess formation, ensuring that the recesses maintain proper geometry and that epitaxial source/drain regions grow with minimal angle relative to the fin top surface, thereby ensuring contact reliability.
3Device complexity
If isolation bumps are formed without sidewall spacers, then manufacturing complexity is reduced, but lateral etching occurs, compromising control over final shape
Solution Approach 1:
Sidewall spacers serve as intermediary protective structures that temporarily remain on the isolation bumps during the etching process. These spacers prevent unwanted lateral etching, ensuring that the isolation bumps maintain their intended shape and size. After the etching is complete, the spacers are removed, having served their protective function. This approach adds minimal complexity while significantly improving shape control.
4Ease of manufacture
If epitaxial source/drain regions are formed with significant angle, then source/drain recess formation is simplified, but source/drain contacts cannot reach the source/drain regions
Solution Approach 1:
Sidewall spacers act as intermediary protective structures during source/drain recess etching. By preventing lateral etching, they ensure that the recess walls remain vertical or near-vertical, which allows epitaxial source/drain regions to grow with minimal angle relative to the fin top surface. This maintains ease of manufacture while ensuring that subsequent source/drain contacts can reliably reach the epitaxial regions.
Data Source
AI summary
Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.