FinFET Overlap Capacitance Reduction via Isolation Structures
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Solution Overview
Problem
The scaling down of FinFET devices leads to challenges in accurately contacting source and drain regions and increased parasitic capacitance due to overlap regions, affecting transistor performance.
Innovation Solution
A method involving the formation of a FinFET structure with silicon substrate-based semiconducting fins, epitaxial source and drain regions, and a conformal gate, along with isolation structures between the source/drain and gate, reducing overlap capacitance and enhancing mechanical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET device size is reduced to increase density, then manufacturing precision and feature shape control become more difficult
Solution Approach 1:
The device is segmented into multiple fins within a single device structure, allowing the channel to be divided into multiple parallel pathways. This segmentation enables better control of current flow and electric field distribution, improving manufacturing precision while maintaining high density through multi-fin configurations
Solution Approach 2:
The invention transitions from planar 2D channel structure to three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change provides better gate control over the channel and improves feature shape accuracy through vertical confinement, enabling higher device density without sacrificing manufacturing precision
2Productivity
If gate structure size is reduced to increase device density, then overlap capacitance increases and transistor performance deteriorates
Solution Approach 1:
The harmful overlap capacitance effect is extracted and isolated by introducing dedicated isolation structures between the gate and source/drain regions. These isolation structures remove the parasitic capacitance pathway while preserving the necessary electrical connections, allowing reduced gate size without performance loss
Solution Approach 2:
Isolation structures serve as intermediary elements positioned between the gate structure and source/drain regions. These intermediaries reduce overlap capacitance by providing electrical isolation while maintaining mechanical support and structural integrity, enabling higher device density with acceptable transistor performance
3Reliability
If source and drain regions are contacted more accurately to improve device performance, then device complexity increases
Solution Approach 1:
Isolation structures are formed preliminarily before final source and drain contact formation. This preliminary action defines the contact regions and provides mechanical support in advance, simplifying subsequent fabrication steps and improving contact accuracy without significantly increasing overall device complexity
Solution Approach 2:
Isolation structures act as intermediary elements that facilitate accurate source and drain contacting by providing defined contact windows and mechanical support. These intermediaries simplify the contacting process while improving reliability through better alignment and structural definition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in optimized AC characteristics and performance by minimizing source/drain to gate capacitance and allowing for reduced gate-to-gate distance, thereby improving mechanical stability and transistor efficiency.
Implementation Method 1
growing a silicon epitaxial layer from a silicon substrate
Data Source
AI summary
Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET.