FinFET Isolation Structure for Stress-Balanced Channel Control
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving improved integration, reliability, and performance, particularly in scaling techniques for multi-gate transistors, where the short channel effect and stress application to active patterns complicate the fabrication process and affect device performance.
Innovation Solution
The semiconductor device incorporates a field insulating film and an element isolation structure with different materials, where the element isolation structure extends across active patterns and field insulating films, applying compressive stress to PMOS channels while preventing deterioration of NMOS performance by using a tensile stress from the field insulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are used for scaling, then integration density is improved, but short channel effect worsens
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional FinFET structures, where the channel is formed as a vertical fin extending from the substrate. This dimensional change allows the gate to control the channel from three sides, improving current control and suppressing short channel effects while enabling higher integration density.
Solution Approach 2:
The patent employs composite material structures including high-k dielectric materials for the gate insulator and metal gate electrodes, combined with selectively doped semiconductor regions. This composite approach enables better electrical control and reduced leakage currents, addressing short channel effects while maintaining scaling benefits.
2Ease of manufacture
If element isolation structure is formed only in active patterns, then manufacturing complexity is reduced, but device performance worsens
Solution Approach 1:
The patent merges the element isolation structure formation with the field insulator formation process. The same etching and filling operations are used to create both the element isolation regions in active patterns and the field isolation regions between active patterns, reducing manufacturing steps while providing comprehensive stress control for both PMOS and NMOS devices.
Solution Approach 2:
The element isolation structure serves multiple functions: it provides electrical isolation between adjacent active patterns, applies mechanical stress to enhance carrier mobility in both PMOS and NMOS transistors, and maintains structural integrity during subsequent processing steps. This multi-functionality justifies the extended formation process across all active patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the integration, reliability, and performance of semiconductor devices by reducing the short channel effect and maintaining NMOS performance, while simplifying the fabrication process by forming the element isolation structure across both active patterns and field insulating films.
Implementation Method 1
the element isolation structure extends across active patterns and field insulating films, applying compressive stress to PMOS channels
Implementation Method 2
preventing deterioration of NMOS performance by using a tensile stress from the field insulating film
Data Source
AI summary
A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.