FinFET Isolation Structure With Etch Control Layer for CMG Trenches
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Solution Overview
Problem
The challenge in semiconductor manufacturing is controlling the etch depth of isolation trenches during the cut-metal-gate (CMG) process, which can damage the substrate and induce current leakage paths between finFETs.
Innovation Solution
The introduction of an etch control layer with a lower etch selectivity than the gate structures prevents isolation trenches from extending into the substrate, allowing for precise control of etch depth and reducing the risk of substrate damage and current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the etch depth of isolation trenches is increased to fully isolate gate structures, then isolation effectiveness is improved, but substrate damage and current leakage paths are induced
Solution Approach 1:
A new etch control layer is introduced as an intermediary between the substrate and gate structures. This layer acts as a mediator that stops the etching process before it reaches the substrate, preventing substrate damage while still achieving complete isolation of the gate structures. The etch control layer is specifically designed with etch selectivity that allows it to be etched faster than the gate structures, enabling precise depth control.
Solution Approach 2:
The etch control layer is formed in advance before the isolation trench etching process. By pre-positioning this layer at the desired etch stop depth, the system prepares a predetermined barrier that automatically limits the etch depth during subsequent processing, eliminating the need for complex real-time depth control while preventing substrate damage.
2Ease of manufacture
If conventional etching processes are used without an etch control layer, then manufacturing simplicity is maintained, but etch depth control precision deteriorates
Solution Approach 1:
The etch control layer serves as a built-in intermediary that provides automatic etch depth control through its etch selectivity properties. This approach maintains manufacturing simplicity because the layer is formed using standard deposition and patterning processes, and it automatically stops etching at the correct depth without requiring complex process control or multiple etching steps.
Solution Approach 2:
The invention utilizes etch selectivity parameter differences between materials to achieve precise depth control. The etch control layer is specifically chosen or engineered to have higher etch rate compared to gate structures, allowing the etching process to naturally stop at the desired depth when the control layer is completely removed, providing precise control without adding manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of an etch control layer enhances the precision of etch depth control in isolation trenches, preventing substrate damage and current leakage, thereby improving the performance and reliability of finFETs.
Implementation Method 1
The introduction of an etch control layer with a lower etch selectivity than the gate structures prevents isolation trenches from extending into the substrate, allowing for precise control of etch depth
Data Source
AI summary
A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin structure having a first fin portion and a second fin portion, forming a first dielectric layer on the substrate and on sidewalls of the first fin portion, forming a second dielectric layer on the first dielectric layer, performing an oxidation process on the second fin portion to form an oxide layer, depositing a gate dielectric layer on the oxide layer and on the second dielectric layer, depositing a gate conductive layer on the gate dielectric layer, and forming an isolation structure extending through the gate conductive layer, the gate dielectric layer, and the second dielectric layer.