FinFET Isolation Doping for Continuous Fin Channel Control

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Solution Overview

Problem

The performance of FinFETs needs to be improved due to challenges in channel control and increased likelihood of short-channel effects as feature sizes decrease.

Innovation Solution

A method for forming a semiconductor structure involves removing the dummy gate structure at the isolation region to form an isolation opening, performing first ion doping on the fin below the isolation opening to create an isolation doped region with a different doping type than the source-drain doped region, and filling an isolation structure in the opening, thereby improving the potential energy barrier and preventing conduction currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the channel length is decreased to adapt to smaller feature sizes, then the integration density is improved, but the channel control capability deteriorates and short-channel effects increase

Engineering Contradiction:
Improveintegration densityVSAvoidchannel control capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from a planar MOSFET structure to a three-dimensional FinFET structure. The fin protrudes vertically from the substrate, creating a three-dimensional channel that allows the gate to control the channel from multiple sides (top and two side walls), thereby improving channel control capability while maintaining small feature sizes and high integration density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The channel is segmented into multiple surfaces (top surface and two side walls) that are all controlled by the gate. This segmentation allows the gate voltage to effectively pinch off the channel from multiple directions, suppressing short-channel effects even when the channel length is reduced for higher integration density.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the dummy gate structure is removed at the isolation region to form an isolation opening, then the isolation effect is improved, but the device complexity increases

Engineering Contradiction:
Improveisolation effectVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dummy gate structure is selectively removed only at the isolation region, while being retained in the active device regions. This local modification creates an isolation opening that improves electrical isolation between adjacent devices, while the added process complexity is localized and manageable.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The dummy gate structure is formed preliminarily across the entire fin structure before selective removal. This preliminary formation simplifies subsequent processing by providing a uniform starting point, and the selective removal at the isolation region can be performed using standard photolithography and etching techniques, managing device complexity effectively.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the channel control capability, reduces leakage currents, and improves carrier mobility by maintaining the fin as a continuous structure without the need for a fin cut process, ultimately leading to better performance of FinFETs.

Implementation Method 1

performing first ion doping on the fin below the isolation opening, to form an isolation doped region in the fin

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS12283517B2Method for forming semiconductor structure
Publication Date: 2025.04.22 SEMICON MFG INT (SHANGHAI) CORP
  • US12283517B2 patent drawing
  • US12283517B2 patent drawing
  • US12283517B2 patent drawing

AI summary

A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, a dummy gate structure, a source-drain doped region, and an interlayer dielectric layer; removing the dummy gate structure located at an isolation region to form an isolation opening; performing first ion doping on a fin below the isolation opening, to form an isolation doped region, where a doping type of the isolation doped region is different from a doping type of the source-drain doped region; filling an isolation structure in the isolation opening; removing the remaining dummy gate structure, to form a gate opening; and forming a gate structure in the gate opening. In embodiments and implementations of the present disclosure, the isolation doped region with a doping type different from that of the source-drain doped region is formed, so that a doping concentration of opposite-type ions in the fin of the isolation region can be improved, thereby accordingly improving a potential energy barrier of a P-N junction formed by the source-drain doped region and the fin of the isolation region, to prevent a conduction current from being generated in the fin of the isolation region when a device is working, and implementing isolation between the fin in the isolation region and the fin in other regions. Moreover, there is no need to perform a fin cut process, so that the fin is a continuous structure, to prevent stress release in the fin.