FinFET Isolation Structure for Adjacent Source/Drain Leakage
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Solution Overview
Problem
As semiconductor devices become more integrated, the challenge of suppressing short-channel effects and reducing channel-leakage currents in FinFETs is exacerbated by the inability to correspondingly reduce the thickness of gate dielectric layers and operating voltage, leading to poor performance due to insufficient isolation between adjacent source/drain doped regions.
Innovation Solution
A method for fabricating a semiconductor structure involving a substrate with an isolation region and device regions, where a sacrificial gate is used to form a first opening in the fin, and an insulation structure is placed within this opening, ensuring its top surface is flush with or higher than the source/drain doped regions, thereby enhancing electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between adjacent fin field effect transistors is decreased to meet integration requirements, then device integration density is improved, but electrical isolation between adjacent source/drain doped regions deteriorates
Solution Approach 1:
The isolation structure is segmented into multiple portions: a first isolation structure in the first opening and a second isolation structure in the second opening. This segmentation allows each isolation structure to independently provide electrical isolation for adjacent source/drain doped regions, ensuring reliable isolation even when the distance between transistors is decreased for higher integration density.
Solution Approach 2:
Different isolation structures are provided at different locations: the first isolation structure is located between source/drain doped regions of adjacent fins, while the second isolation structure is located between source/drain doped regions of adjacent device regions. This local differentiation ensures that electrical isolation is optimized at each specific location where it is needed, maintaining reliability while enabling higher integration.
2Ease of manufacture
If a simple isolation structure is used between adjacent source/drain doped regions, then manufacturing complexity is reduced, but isolation effectiveness deteriorates
Solution Approach 1:
The sacrificial gate structure is formed in advance at the isolation region before the isolation structures are formed. This preliminary action defines the positions of the first and second openings, ensuring that the isolation structures will be precisely located between the source/drain doped regions. This approach simplifies the overall manufacturing process by establishing a clear fabrication sequence while ensuring effective isolation.
Solution Approach 2:
The sacrificial gate structure serves as an intermediary element that temporarily occupies the isolation region during fabrication. It acts as a placeholder that defines the geometry and position of the isolation structures, which are formed after the sacrificial gate is removed. This intermediary approach simplifies the formation of precisely positioned isolation structures while ensuring they provide effective electrical isolation.
Data Source
AI summary
Semiconductor structure is provided. The semiconductor structure includes a substrate including device regions and an isolation region located adjacent to and between the device regions; a fin on the substrate; gate structures across the fin at the device regions; source/drain doped regions in the fin at two sides of each of the gate structures; a first opening in the fin at the isolation region; and an insulation structure located in the first opening. Two opposite sidewalls of the first opening are respectively in contact with the source/drain doped regions at adjacent device regions. A top surface of the insulation structure is flush with or higher than top surfaces of the source/drain doped regions.