FinFET Isolation Section Self-Aligned to Dummy Gate Spacer
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in reducing the area occupied by isolation sections in miniaturized devices, particularly in FinFETs, where multiple dummy gates are required, leading to increased costs and reduced device density.
Innovation Solution
A semiconductor arrangement and manufacturing method that self-aligns an isolation section to the space defined by a dummy gate spacer, allowing for the use of a single dummy gate and reducing the footprint of the isolation section, applicable to FinFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple dummy gates are used for isolation in FinFETs, then electrical isolation between devices is achieved, but the area occupied by isolation sections increases
Solution Approach 1:
The patent extracts the isolation function from the traditional multi-dummy-gate structure and concentrates it into a single dummy gate positioned between adjacent FinFETs. This single dummy gate, combined with the fin structure, provides the necessary electrical isolation while occupying significantly less area than the conventional approach requiring two dummy gates per isolation section.
Solution Approach 2:
The patent merges the isolation function with the fin structure itself. The fin acts as both the active device component and part of the isolation structure, eliminating the need for separate isolation regions. The single dummy gate works in conjunction with the fin to provide both device functionality and electrical isolation.
2Productivity
If more devices are integrated on a wafer, then device density increases, but the area available per device decreases
Solution Approach 1:
The patent utilizes the vertical dimension through the fin structure to achieve device functionality, allowing the device to extend in the height direction rather than requiring more lateral space. This 3D architecture enables higher device density on the wafer surface while maintaining adequate isolation between adjacent devices.
Solution Approach 2:
The patent applies isolation structures only where electrically necessary - specifically at the interfaces between adjacent FinFETs - rather than using uniform isolation across the entire device area. The single dummy gate provides localized isolation precisely where needed, minimizing the area penalty while ensuring proper electrical separation.
3Ease of manufacture
If traditional isolation methods are used in miniaturized devices, then manufacturing process is well-established, but area penalty and manufacturing cost increase
Solution Approach 1:
The single dummy gate is formed during the standard FinFET manufacturing process at an early stage, before the final device structures are completed. This preliminary placement of the dummy gate allows subsequent processing steps to naturally form the isolation regions without requiring additional complex steps, maintaining manufacturing simplicity while reducing area.
Solution Approach 2:
The single dummy gate serves multiple functions simultaneously: it acts as a placeholder for future device formation, provides electrical isolation between adjacent FinFETs, and defines the boundary for isolation region formation. This multi-functionality eliminates the need for separate dedicated isolation structures, reducing area while maintaining manufacturing ease.
Data Source
AI summary
A semiconductor arrangement and a method for manufacturing the same. An arrangement may include a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate. The first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack. The second FinFET includes a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; an isolation section self-aligned to a space defined by the dummy gate spacer. The isolation section electrically isolates the first FinFET from the second FinFET; and an insulation layer disposed under and abutting the isolation section.