FinFET Isolation Layout Using a Self-Aligned Dummy Gate Spacer
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Solution Overview
Problem
Current semiconductor technologies face challenges in reducing the area penalty for integrating more devices on a chip, particularly due to increased space occupied by isolation between FinFETs, which hinders further miniaturization and increases costs.
Innovation Solution
A semiconductor arrangement and manufacturing method that includes a self-aligned isolation section using a dummy gate spacer, reducing the need for multiple dummy gates and allowing an additional isolation section underneath, thereby minimizing footprint and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFETs are used to reduce footprint on chip surface by extending in height direction, then device integration density is improved, but area occupied by isolation between FinFETs increases due to requirement of two dummy gates per isolation
Solution Approach 1:
The patent merges the isolation structure with the dummy gate structure by forming the isolation section within the space defined by the dummy gate spacer. This integration eliminates the need for separate isolation structures, reducing the total area occupied by isolation while maintaining electrical isolation functionality between adjacent FinFETs.
Solution Approach 2:
The patent extends the isolation section into the vertical dimension by forming a second isolation section under the bottom surface of the first isolation section. This multi-layer isolation approach provides effective electrical isolation while minimizing the horizontal footprint on the chip surface.
2Adaptability or versatility
If more devices are integrated on a chip for a given area to meet multi-functional miniaturized electronic device demands, then device functionality is improved, but area penalty increases leading to increased cost
Solution Approach 1:
The patent combines the isolation function with the dummy gate spacer structure, allowing the isolation section to be formed within the same lateral space as the dummy gate spacer. This merging reduces the area penalty associated with isolation structures, enabling more devices to be integrated on a chip for a given area.
3Manufacturing precision
If self-aligned isolation section is formed using dummy gate spacer, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent forms the dummy gate spacer structure before forming the isolation section, using the dummy gate spacer as a pre-established reference structure. This preliminary action enables self-aligned formation of the isolation section, improving alignment precision while the systematic process flow manages the overall process complexity.
Data Source
AI summary
Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.