FinFET Isolation Structure Etching With Tilted Ion Implantation
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Solution Overview
Problem
In the formation of FinFET devices, seams (air pockets) in the dielectric material filling trenches between fin elements can cause uneven etching, leading to performance uniformity issues in the FinFET devices.
Innovation Solution
A method involving tilted ion implantation is applied to the top portions of the isolation structure, compensating for the etch rate difference of the dielectric material on one side of the fin, resulting in consistent average etch rates on both sides of the fin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If trenches are filled with dielectric material to form isolation structures between fin elements, then the FinFET device structure is completed, but seams (air pockets) are formed in the dielectric material causing uneven etching and performance uniformity issues
Solution Approach 1:
The patent applies tilted ion implantation to specific regions of the isolation structure - specifically the top portions and sidewalls adjacent to the fin. This creates localized modifications in the dielectric material properties (increased etch rate) precisely where needed to compensate for the presence of seams, rather than uniformly treating the entire isolation structure. The selective application to affected regions resolves the etching uniformity problem while maintaining the integrity of the overall device structure.
Solution Approach 2:
The ion implantation process is performed as a preliminary step before the dielectric material recess process. By pre-modifying the dielectric material properties through ion implantation, the patent prepares the isolation structure to etch uniformly during the subsequent recess process, even in the presence of seams. This preliminary action prevents the performance uniformity issues that would otherwise arise from uneven etching.
2Productivity
If the width of trenches is reduced to increase functional density, then production efficiency increases and costs decrease, but seams are more frequently formed in the dielectric material
Solution Approach 1:
The patent converts the harmful effect of seams (which cause uneven etching) into a manageable condition by using tilted ion implantation to pre-compensate for their presence. Instead of trying to eliminate the seams entirely, the method accepts their presence but modifies the dielectric material properties around them to ensure uniform etching behavior. This allows continued scaling with reduced trench widths while maintaining etching uniformity.
Solution Approach 2:
The patent changes the physical and chemical parameters of the dielectric material through ion implantation, specifically increasing the etch rate of the implanted regions. By modifying parameters such as ion energy, ion dose, and implantation angle, the process creates localized zones with enhanced etchability that compensate for the reduced trench width and the presence of seams, enabling continued scaling while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the performance uniformity of FinFET devices by ensuring consistent etching of the isolation structure, reducing the impact of seams and improving overall device performance.
Implementation Method 1
A method involving tilted ion implantation is applied to the top portions of the isolation structure, compensating for the etch rate difference of the dielectric material on one side of the fin
Data Source
AI summary
A method includes forming a semiconductor fin protruding from a substrate and depositing a dielectric layer over the substrate. The dielectric layer has a first portion deposited on a first sidewall of the semiconductor fin and a second portion deposited on the second sidewall of the semiconductor fin. The method further includes implanting impurities into the first and second portions of the dielectric layer. The impurities reach a first depth in the first portion of the dielectric layer and a second depth in the second portion of the dielectric layer. The first depth is smaller than the second depth. The method further includes recessing the dielectric layer to expose the first and second sidewalls of the semiconductor fin.