FinFET Isolation Fill Using Thinned Oxide Liner to Prevent Voids

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Solution Overview

Problem

The semiconductor industry faces challenges in fabricating FinFETs with high integration density due to voids in insulation fill material deposition between semiconductor fins, leading to reduced yield and increased fabrication costs.

Innovation Solution

The formation of an oxide liner over semiconductor fins with a post-deposition treatment to reshape and thin it, allowing for the deposition of insulation fill material without voids, thereby improving the filling efficiency of recesses between fins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If insulation fill material is deposited between semiconductor fins without oxide liner thinning, then deposition process is simpler and faster, but voids form in the insulation material reducing yield

Engineering Contradiction:
Improvedeposition speedVSAvoidyield
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The oxide liner is thinned before insulation material deposition to prevent void formation. This preliminary action modifies the liner geometry in advance, ensuring that subsequent insulation material can be deposited without creating voids, thus resolving the contradiction between deposition speed and yield.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The oxide liner thickness is selectively reduced in specific regions (where voids would form) while maintaining original thickness in other areas. This localized modification allows insulation material to deposit properly in critical regions without requiring complete liner removal, balancing productivity and reliability.

Inventive Principle:
Principle #3Local quality

2Reliability

If oxide liner is thinned to prevent voids, then insulation material fills recesses completely improving yield, but additional process steps increase fabrication complexity

Engineering Contradiction:
ImproveyieldVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The oxide liner thickness parameter is modified through controlled thinning processes. By adjusting deposition or etching parameters, the liner thickness is optimized to prevent void formation while minimizing the number of additional process steps required, thus improving yield without excessive complexity increase.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The oxide liner serves as an intermediary layer whose thickness is controlled to mediate between the fin structure and insulation material. By thinning this intermediary layer selectively, void formation is prevented while the overall process remains integrated into the existing fabrication flow, limiting complexity increases.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Strength

If oxide liner thickness is increased, then liner provides better protection and structural support, but insulation material deposition creates more voids reducing filling efficiency

Engineering Contradiction:
Improveliner protectionVSAvoidfilling efficiency
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The oxide liner thickness is varied locally - thicker in regions requiring structural support and protection, thinner in regions where insulation material deposition occurs. This spatial variation maintains liner strength where needed while preventing void formation in deposition zones, resolving the contradiction between protection and filling efficiency.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The oxide liner thickness is pre-adjusted in specific regions before insulation material deposition. By performing this thickness modification in advance, the liner maintains adequate protection in general while having optimized geometry in critical areas to prevent voids, thus balancing strength and manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the yield and efficiency of semiconductor device fabrication, reducing costs by ensuring the insulation fill material is deposited free of voids, resulting in improved semiconductor device performance.

Implementation Method 1

depositing an oxide liner along the first fin, the second fin, and the semiconductor substrate

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

depositing an oxide liner along the first fin, the second fin, and the semiconductor substrate

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

performing a plasma process on the oxide layer

Methodology Applied
Scientific EffectPlasma: Plasma

Implementation Method 4

performing a plasma process on the oxide layer

Methodology Applied
Scientific EffectSputtering: Sputtering

Implementation Method 5

performing a plasma process on the oxide layer

Methodology Applied
Scientific EffectChemical Etching:

Implementation Method 6

depositing an insulation material over the oxide liner

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS20240186190A1Semiconductor Device and Methods of Forming the Same
Publication Date: 2024.06.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240186190A1 patent drawing
  • US20240186190A1 patent drawing
  • US20240186190A1 patent drawing

AI summary

In an embodiment, a method includes: forming a first fin and a second fin over a semiconductor substrate; forming an isolation region between the first fin and the second fin, forming the isolation region comprising: depositing an oxide liner along the first fin, the second fin, and the semiconductor substrate, the oxide liner comprising a first upper portion and a first lower portion along the first fin, the first lower portion being between the first upper portion and the semiconductor substrate; thinning the oxide liner; depositing an insulation material over the oxide liner; and recessing the insulation material; and forming a gate structure over the first fin, the second fin, and the isolation region.