FinFET Isolation Gate Layout for Leakage Current Control
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Solution Overview
Problem
As semiconductor devices integrate at higher levels, reducing transistor sizes complicates the suppression of short channel effects and increases channel leakage current due to unchanged dielectric layer thickness and operation voltage, and existing isolation methods like SDB and DDB face challenges in achieving effective electrical isolation without impacting integration level and performance.
Innovation Solution
A semiconductor structure with first active regions, isolation regions, fins spanning adjacent active and isolation regions, gate structures over isolation regions, and electrical interconnection structures connected to the gate structures, allowing for electrical isolation without removing the gate structures, thus avoiding layout-dependent effects and improving integration level and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor sizes are reduced to increase integration level, then integration level is improved, but channel leakage current increases and short channel effects become harder to suppress
Solution Approach 1:
The isolation region is segmented into multiple regions along the channel direction, with each segment having its own gate structure (first gate structure, second gate structure, third gate structure). This segmentation allows independent control of leakage current in different isolation regions, effectively suppressing short channel effects while maintaining high integration level through continued scaling of transistor dimensions.
2Productivity
If isolation layer area is reduced to improve integration level, then integration level is improved, but electrical isolation effectiveness may be compromised
Solution Approach 1:
The gate structures extend not only in the lateral direction but also in the vertical direction, forming a three-dimensional configuration that spans across the isolation region. This dimensional extension allows effective electrical isolation with reduced planar area, as the gate structures can control leakage current through their vertical presence rather than requiring large lateral isolation layer area.
3Reliability
If gate structures are removed from isolation regions to achieve electrical isolation, then electrical isolation is improved, but layout-dependent effects increase and integration level decreases
Solution Approach 1:
Instead of removing gate structures from isolation regions as in conventional approaches, this invention retains and utilizes gate structures on the isolation region. The gate structures are configured to control leakage current through their electrical connection to source and drain regions, inverting the conventional wisdom that isolation requires gate removal. This approach reduces layout-dependent effects while maintaining effective electrical isolation.
Data Source
AI summary
A semiconductor structure includes a substrate including a first region. The first region includes a plurality of first active regions arranged along a first direction and a first isolation region between the adjacent first active regions. The semiconductor structure also includes a plurality of first fins on the substrate, parallel to the first direction and arranged along a second direction. The second direction is perpendicular to the first direction. The first fins span the adjacent first active regions and the first isolation region between the first active regions. The semiconductor structure also includes a plurality of first gate structures in the first isolation region. The first gate structures span the first fins along the second direction. The semiconductor structure also includes a plurality of first electrical interconnection structures, electrically connected to the first gate structures.